BD9329AEFJ_15 Datasheet, PDF (9/23 Pages) Rohm – Synchronous Buck Converter with Integrated FET

BD9329AEFJ
2. Block Operation
(1) VREG
This block generates a constant voltage for DC/DC boosting.
(2) VREF
This block generates an internal reference voltage of 5.1V (Typ).
(3) TSD/UVLO
TSD (Thermal shutdown)/UVLO (Under Voltage Lockout) protection block.
The TSD circuit shuts down the IC at high temperature.
The UVLO circuit shuts down the IC when the VIN voltage is low.
(4) Error Amp Block (ERR)
This block compares the reference voltage and the feedback voltage from the output. The output voltage of this block,
which is connected to COMP pin, determines the switching duty cycle. At the time of startup, since the soft-start is
operated by the SS pin voltage, the COMP pin voltage is limited to the SS pin voltage.
(5) Oscillator Block (OSC)
This block generates the oscillating frequency.
(6) SLOPE Block
This block generates the triangular waveform with the use of the clock created by OSC. The generated triangular
waveform is sent to the PWM comparator.
(7) PWM Block
The COMP pin voltage output of the error amp is compared with the SLOPE block's triangular waveform to determine
the switching duty. Since the switching duty cycle is limited by the maximum duty ratio which is determined internally,
100% duty cycle cannot be achieved.
(8) DRV Block
This is the A DC/DC driver block that accepts signal from the PWM block to drive the power FETs.
(9) OCP Block
OCP (Over Current Protection) block. The current that flows through the FETs is detected, and OCP starts when it
reaches 3.5A (min). After OCP detection, switching is turned OFF and the SS capacitor is discharged. OCP is
self-recovery type (not latch).
(10) Soft-Start Circuit
This circuit prevents output voltage overshoot or inrush current by making the output voltage rise gradually while
restricting the current at the time of startup.
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TSZ22111・15・001
9/19
TSZ02201-0323AAJ00010-1-2
16.Feb.2015 Rev.003