BD9329AEFJ_15 Datasheet, PDF (13/23 Pages) Rohm – Synchronous Buck Converter with Integrated FET

BD9329AEFJ
6. Layout Pattern Consideration
Two high pulsing current loops exist in the buck regulator system. The first loop, when FET is ON, starts from the input
capacitors, to the VIN terminal, to the SW terminal, to the inductor, to the output capacitors, and then returns to the input
capacitor through GND. The second loop, when FET is OFF, starts from the low FET, to the inductor, to the output capacitor,
and then returns to the low FET through GND. To reduce the noise and improve the efficiency, please minimize these two
loop areas. The input capacitor, output capacitor, and the low FET should be connected to the PCB’s GND plain. PCB
Layout may greatly affect the thermal performance, noise, and efficiency. So, please take extra care when designing PCB
Layout patterns.
VIN
CIN
FET
L
VOUT
COUT
Figure 26. Current Loop in Buck Regulator System
(1) The thermal Pad on the back side of the IC offers great thermal conduction to the chip. So, using the GND plain on the
PCB as broad and wide as possible can help thermal dissipation. And a lot of thermal via for helping the spread of heat
to the different layers is also effective.
(2) The input capacitors should be connected as close as possible to the VIN terminal.
(3) When there is an unused area on the PCB, please arrange the copper foil plain of DC nodes, such as GND, VIN and
VOUT for better heat dissipation of the IC or circumference parts.
(4) To avoid the noise influence from AC coupling with the other lines, keep the switching lines such as SW as short as
possible, and coil traces as short and as thick as possible.
(5) Keep sensitive signal traces such as traces connected to FB and COMP away from SW pin.
(6) The inductor and the output capacitors should be placed close to SW pin as much as possible.
CIN
BST
VIN
SW
GND
L
COUT
VOUT
SS
EN
COMP
FB
Figure 27. The Example of PCB Layout Pattern
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TSZ22111・15・001
13/19
TSZ02201-0323AAJ00010-1-2
16.Feb.2015 Rev.003