BD9560MUV_09 Datasheet, PDF (8/22 Pages) Rohm – Switching Regulator Controller for Graphic Chip Cores

BD9560MUV
Technical Note
●Pin Descriptions
・VCC
This is the power supply pin for IC internal circuits, except the FET driver. The input supply voltage range is 4.5V to
5.5V. It is recommended that a 1uF bypass capacitor be put in this pin.
・VRON
When VRON pin voltage at least 2.3V, the status of this switching regulator become active. Conversely, the status
switches off when VRON pin voltage goes lower than 0.8V and circuit current becomes 10µA or less.
・VREF
This is the reference voltage output pin. The voltage is 2.5V, with 100µA current ability. It is recommended that a 0.1uF
capacitor be established between VREF and GND.
・CL
BD9560MUV detects the voltage between ISP pin and ISM pin and limits the output current (OCP) voltage equivalent to 1/16 of
the CL voltage drop of external current sense resistor. A very low current sense resistor or inductor DCR can also be used for
this platform.
・SS
This is the adjustment pin to set the soft start time. SS voltage is low during shutdown status. When VRON is the status
of high, the soft start time can be determined by the SS charge current and capacitor between SS and GND. Until SS
reaches DAC output voltage, the output voltage VOUT is equivalent to SS voltage.
・SCP
This is the pin to adjust the timer latch time for short circuit protection. The timer circuit is active when the output
voltage VOUT becomes 70% of DAC output voltage, and the output switches OFF (HG=L, LG=L) and is latched after
the specified time. When the UVLO circuit is active or VRON is low, this latch function is cancelled.
・VIN
Since the VIN line is also the input voltage of switching regulator, stability depends in the impedance of the voltage
supply. It is recommended to establish a bypass capacitor or CR filter suitable for the actual application.
・TON
This is the adjustment pin to set the ON time. On time is determined by the applied voltage to TON pin.
・ISP, ISM
These pins are connected to both sides of the current sense resistor detect output current. The voltage drop between ISP and
ISM is compared with the voltage equivalent to 1/16 of CL voltage. When this voltage drop hits the specified voltage level, the
output voltage is OFF. And these are the pins returned output voltage for Power Good block, SCP block and OVP block.
・BOOT
This is the voltage supply to drive the high side FET. The maximum absolute ratings are 35V (from GND) and 7V (from
SW). BOOT voltage swings between (VIN+VCC) and VCC during active operation.
・HG
This is the voltage supply to drive the Gate of the high side. This voltage swings between BOOT and SW. High-speed Gate driving
for the high side FET is achieved due to the low on-resistance (1.5 ohm when HG is high, 1.0 ohm when HG is low) driver.
・SW
This is the source pin for the high side FET. The maximum absolute ratings are 30V (from GND). SW voltage swings between
VIN and GND.
・PVCC
This is the power supply to drive the low side FET Gate. It is recommended that a 10uF bypass capacitor be
established to compensate for rush current during the FET ON/OFF transition.
・LG
This is the voltage supply to drive the Gate of the low side FET. This voltage swings between PVCC and PGND.
High–speed Gate driving for the low side FET is achieved due to the low on-resistance (1.5 ohm when LG is high, 0.5
ohm when LG is low) driver.
・PGND
This is the power ground pin connected to the source of the low side FET.
・PWRGD
This is the Power Good output pin with open drain. When VOUT range is (VDAC-300mV) to (VDAC+200mV), the
status is high, and when it is in out of range, the status is low.
・PWRGD_C
This is the pin to adjust the delay time of Power Good. When the status of the output voltage is Power Good, the delay
time is determined by the capacitor connected between the fixed current for internal IC and PWRGD_C-GND.
・SLLM
This is the adjustment pin to set the control mode. When SLLM pin voltage goes lower than 0.5V, the status is continuous
mode. Conversely the status is SLLM (Simple Light Load Mode) when SLLM pin voltage is at least (VCC-0.5).
・VID[0:4]
This is the logic input pin for 5bit DAC.
・LSP, LSM
This is the input pin for the amplifier to set the load slope.
・SUS_OUT
The output is SUS_OUT=”H” in performance states, is SUS_OUT=”L” in sleep states.
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2009.04 - Rev.B