BD9130EFJ Datasheet, PDF (8/15 Pages) Rohm – Output 2A or More High-efficiency Step-down Switching Regulator with Built-in Power MOSFET

BD9130EFJ
Technical Note
●Switching regulator efficiency
Efficiency ŋ may be expressed by the equation shown below:
η= ^VOUT×IOUT ×100[%]= ^POUT ×100[%]=
Vin×Iin
Pin
POUT
POUT+PDα
×100[%]
Efficiency may be improved by reducing the switching regulator power dissipation factors P_Dα as follows:
Dissipation factors:
1) ON resistance dissipation of inductor and FET：PD(I²R)
2) Gate charge/discharge dissipation：PD(Gate)
3) Switching dissipation：PD(SW)
4) ESR dissipation of capacitor：PD(ESR)
5) Operating current dissipation of IC：PD(IC)
1)PD(I²R)=IOUT²Ã—(RCOIL+RON) (RCOIL[Ω]：DC resistance of inductor, RON[Ω]：ON resistance of FET, IOUT[A]：Output current.)
2)PD(Gate)=Cgs×f×V (Cgs[F]：Gate capacitance of FET、f[H]：Switching frequency、V[V]：Gate driving voltage of FET)
3)PD(SW)=
Vin²Ã—CRSS×IOUT×f
IDRIVE
(CRSS[F]：Reverse transfer capacitance of FET、IDRIVE[A]：Peak current of gate.)
4)PD(ESR)=IRMS²Ã—ESR (IRMS[A]：Ripple current of capacitor、ESR[Ω]：Equivalent series resistance.)
5)PD(IC)=Vin×ICC (ICC[A]：Circuit current.)
●Consideration on permissible dissipation and heat generation
As this IC functions with high efficiency without significant heat generation in most applications, no special consideration is
needed on permissible dissipation or heat generation. In case of extreme conditions, however, including lower input
voltage, higher output voltage, heavier load, and/or higher temperature, the permissible dissipation and/or heat generation
must be carefully considered.
For dissipation, only conduction losses due to DC resistance of inductor and ON resistance of FET are considered.
Because the conduction losses are considered to play the leading role among other dissipation mentioned above including
gate charge/discharge dissipation and switching dissipation.
4.0
⑤3.76W
3.0
④2.11W
2.0
③1.10W
1.0 ②0.82W
①0.50W
① IC only
θj-a=249.5℃/W
②1 layers（copper foil area:0mm×0mm）
θj-a=153.2℃/W
③2 layers（copper foil area:15mm×15mm）
θj-a=113.6℃/W
④2 layers（copper foil area:70mm×70mm）
θj-a=59.2℃/W
⑤4 layers（copper foil area:70mm×70mm）
θj-a=33.3℃/W
(when mounted on a board 70mm×70mm×1.6mm
Glass-epoxy PCB with termal Via)
P=IOUT²Ã—RON
RON=D×RONP+(1-D)RONN
D：ON duty (=VOUT/VCC)
RCOIL：DC resistance of coil
RONP：ON resistance of P-channel MOS FET
RONN：ON resistance of N-channel MOS FET
IOUT：Output current
0
0
25 50 75 100105 125 150
Ambient temperature:Ta [℃]
Fig.26 Thermal derating curve
(HTSOP-J8)
If VCC=3.3V, VOUT=1.8V, RONP=0.2Ω, RONN=0.16Ω
IOUT=2A, for example,
D=VOUT/VCC=1.8/3.3=0.545
RON=0.545×0.20+(1-0.545)×0.16
=0.109+0.0728
=0.1818[Ω]
P=2²Ã—0.1818＝0.7272W]
As RONP is greater than RONN in this IC, the dissipation increases as the ON duty becomes greater. With the consideration
on the dissipation as above, thermal design must be carried out with sufficient margin allowed.
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8/14
2009.05 - Rev.A