BU9728AKV Datasheet, PDF (7/10 Pages) Rohm – LCD driver for segment-type LCDs

Standard ICs
BU9728AKV
•^{Description of functions}
(1) Register
The BU9728AKV has a command / data register configured of eight bits. Serial data is read in 8-pulse units of the
SCK clock.
If the data read to the register is display data (C / D is LOW at the 8th clock pulse of SCK), it is written to the
DDRAM, and if the data is command data (C / D is HIGH at the 8th clock pulse of SCK), it is output to a command
decoder and used to control the BU9728AKV.
(2) Address counter
The address counter indicates the DDRAM address. When the set address is written to the command / data register,
the address data is automatically sent to the address counter.
After the data is written to the DDRAM, the address counter is automatically incremented by either + 1 or + 2. The
amount by which the counter is incremented is determined automatically, based on the following statuses:
8 bits written to DDRAM (C / D LOW at 8th clock pulse of SCK) → + 2
4 bits written to DDRAM (C / D HIGH at 8th clock pulse of SCK) → + 1
When the address counter reaches 1FH, it will be reset back to 00H the next time it is incremented.
(3) Display Data RAM (DDRAM)
The Display Data RAM (DDRAM) is where displays are stored. The capacity of the DDRAM is 32 addresses × 4 bits.
The illustration below shows the relationship between the DDRAM and the display positions.
0
1
bit
2
DDRAM address
00 01 02 03 04 05 06 07
1D 1E 1F
COM0
COM1
COM2
3
COM3
DDRAM addresses set in the address counter are in hexadecimal format and are indicated as follows.
MSB
LSB
AC4
AC3
AC2
AC1
AC0
(Example) For a DDRAM address of “14” (display position: SEG20)
MSB
LSB
1
0
1
0
0
1
4
7