BU26156RFS Datasheet, PDF (53/95 Pages) Rohm – Monoraul MIC Input with ALC

BU26156RFS
Datasheet
SAI Transmitter Control Register
MAPCON
0x0
INDEX
R
W
0x4c 0x4d
b07
b06
(Initial)
PCMFO24
1
1
b05
FMTO
0
b04
b03
b02
MSBO
0
ISSCKO
0
AFOO
0
b01
DLYO
0
b00
WSLO
0
This register controls the SAI transmit format setting. This register setting must not be changed during SAI operation. Set this
register as same as SAI Receiver Control Register.
WSLO
This bit specifies the LRCLK polarity at this LSI’s transmission. This bit must be set at “1” when the Flame synchronous
transfer mode (FMTO is “1”).
WSLO
Description
0
Left channel transmission at LRCLK is “L” level; right channel transmission at
LRCLK is “H” level.
1
Left channel transmission at LRCLK is “H” level; right channel transmission at
LRCLK is “L” level.
DLYO
This bit specifies the existence for serial output data one clock delay of master device.
DLYO
Description
0
Serial data delay exists
1
No serial data delay
AFOO
This bit specifies left-justify or right-justify. In case of the slave mode, this bit is ignored and fixed at left-justify. This bit must
be set at “0” when the Flame synchronous transfer mode (FMTO is “1”).
AFOO
Description
0
Left-justify
1
Right-justify
ISSCKO
This bit specifies 32fs or 64fs.
ISSCKO
0
32fs
1
64fs
Description
MSBO
This bit specifies MSB-first or LSB-first of the SAI transmission data.
MSBO
Description
0
MSB-first
1
LSB-first
FMTO
This bit specifies transmission mode.
FMTO
Description
0
SAI_LRCLK transfer mode
1
Flame synchronous transfer mode
PCMFO24
This bit specifies PCM format of SAI transmission data.
PCMFO24
Description
0x2
16bit PCM
0x3
24bit PCM
Other
Prohibited
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TSZ02201-0V1V0E502570-1-2
Jul.1.2014 Rev.001