BU26156RFS Datasheet, PDF (41/95 Pages) Rohm – Monoraul MIC Input with ALC

BU26156RFS
Datasheet
Clock Input/Output Control Register
MAPCON
INDEX
b07
b06
b05
b04
b03
b02
b01
b00
R
W
(Initial)
0x0
0x0e 0x0f
-
-
-
PLLISEL(*)
CLKSEL(*)
-
-
-
0
0
0
0
0
This register is to select internal clock. It is to use or not use and to create MCLKI input or internal clock divided PLL.
CLKSEL[2:0]
These bits are to select the internal clock.
CLKSEL[2:0]
Description
0x0
Use PLL output clock.(256fs)
0x2
Use PLL output clock.(512fs)
PLL output clock is divided by 2 in the LSI.
0x3
Use PLL output clock.(1024fs)
PLL output clock is divided by 4 in the LSI.
0x4
256fs external clock from MCLKI pin input.
MCLKI pin input is directly used in the LSI.
0x6
512fs external clock from MCLKI pin input.
MCLK pin input is divided by 2 in the LSI.
0x7
1024fs external clock from MCLKI pin input.
MCLK pin input is divided by 4 in the LSI.
PLLISEL[1:0]
This bit is to select the input clock to Audio PLL. If not use PLL, it is to set 0x0.
PLLISEL[1:0]
Description
0x0
Use LRCLK input pin
0x1
Use MCLKI input pin
0x2
Use BCLK input pin
Software Reset Register
MAPCON
INDEX
b07
b06
b05
b04
b03
b02
b01
b00
R
W
(Initial)
0x0
0x10 0x11
-
-
-
-
-
-
-
SOFTRST(*)
-
-
-
-
-
-
-
0
This register is for software reset. CPU interface and this register are reset by writing SOFTRST bit to “1”. And then, write “0”
for releasing reset.
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TSZ22111・15・001
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TSZ02201-0V1V0E502570-1-2
Jul.1.2014 Rev.001