BU90T82_16 Datasheet, PDF (5/29 Pages) Rohm – 27bit LVDS Dual-out Transmitter

BU90T82
Datasheet
Pin Description
Pin name
TA1+/-, TB1+/-,
TC1+/-,TD1+/-
TCLK1+/-
TA2+/-, TB2+/-,
TC2+/-,TD2+/-
TCLK2+/-
R1[7:0]
G1[7:0]
B1[7:0]
DE
HSYNC
VSYNC
Pin NO.
A1,B1,A2,B2,A3,B3,A5,B5
A4,B4
A6,B6,A7,B7,A8,B8,C9,C8
A9,B9
G1,G2,F1,F2,E1,E2,D1,D2
J4,H4,J3,H3,J2,H2,J1,H1
J8,H8,J7,H7,J6,H6,J5,H5
G9
J9
H9
Type
LVDS output
LVDS output
LVCMOS input
LVCMOS input
Descriptions
LVDS Data output (Channel1)
LVDS Clock output (Channel1)
LVDS Data output (Channel2)
LVDS Clock output (Channel2)
Pixel data input
Control data input
CLKIN
F9
PWDN
D8
OE
D9
RF
G8
RS
F8
MAP
E8
MODE
E7
DDRN
E9
6B8B
F7
FLIP
C2
TEST
C3
LVCMOS input Clock input
LVCMOS input
Power Down
H：Normal operation
L：Power down (all LVDS output signal are Hi-z)
LVDS Output Enable.
H: Output enable
L: Output disable(all LVDS output signal are Hi-z)
Input CLK Triggering Edge Select.
H：Rising edge
L：Falling edge
LVDS Swing Mode Select
H: 350mV
L: 200mV
LVDS Output Data Mapping Select
H: JEIDA
L: VESA
LVDS Output Mode Select
H: Single in / Single out
L: Single in / Dual out
(MODE=H, DDRN=L Distribution out)
Input CLK Triggering Edge Select.
H: DDR function disable
L: DDR function enable
(It is possible only at Dual-out mode)
(MODE=H, DDRN=L Distribution out)
6bit/8bit Mode Select
H : 6bit mode (TD1+/-, TD2+/- outputs are Hi-z)
L : 8bit mode
LVDS Output Pin Reverse Select.
H: Reverse
L/Open: Normal
TEST Mode Select (Normal operation is Low)
PRBS
C1
PRBS Data Output (Normal operation is Low)
VDD
VDDIO
C5,C7,D3,G3,G5
G7
Power
Power Supply for Internal Core
Power Supply for I/O
GND
C4,C6,D7,E3,F3,G4,G6
Ground
Ground Pins
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TSZ22111 • 15 • 001
5/25
TSZ02201-0L2L0H500270-1-2
06.July.2016 Rev.003