BU90T82_16 Datasheet, PDF (2/29 Pages) Rohm – 27bit LVDS Dual-out Transmitter

BU90T82
Contents
Datasheet
General Description....................................................................................................................................................1
Key Specifications ......................................................................................................................................................1
Package
W(Typ) x D(Typ) x H(Max)....................................................................................................1
Applications ................................................................................................................................................................1
Features .......................................................................................................................................................................1
Block Diagram.............................................................................................................................................................1
Figure 1. Block Diagram .........................................................................................................................................1
Pin Configuration........................................................................................................................................................4
Figure 2. Pin Configuration ....................................................................................................................................4
Pin Description............................................................................................................................................................5
Absolute Maximum Ratings (Ta = 25°C) ...................................................................................................................6
Recommended Operating Conditions (Ta= -40°C to +85°C)...................................................................................6
DC Characteristics......................................................................................................................................................6
AC Characteristics......................................................................................................................................................7
Figure 3. LVDS Output AC Timing Diagrams ........................................................................................................7
Figure 4. LVCMOS Input AC Timing Diagrams .....................................................................................................8
Figure 5. LVCMOS Input AC Timing Diagrams (DDRN=L) ...................................................................................8
LVDS Output AC Timing Diagrams ...........................................................................................................................9
Figure 6. LVDS Output AC Timing Diagrams ........................................................................................................9
Phase Locked Loop Set Time ..................................................................................................................................9
Figure 7. Phase Locked Loop Set Time ................................................................................................................9
Supply Current ..........................................................................................................................................................10
Figure 8. Gray Scale Pattern, Worst Case Pattern .............................................................................................10
LVCMOS Data Inputs Pixel Map Table ....................................................................................................................11
Output Mode Select on MODE, DDRN Pins............................................................................................................12
Figure 9. Output Mode Select on MODE,DDRN Pins .........................................................................................12
DE Input Timing Diagrams.......................................................................................................................................12
Figure 10. Dual-out mode DE Input Timing Diagrams (MODE=L) ....................................................................12
Single-in / Single-out Mode......................................................................................................................................13
Figure 11. Single-in / Single-out Mode ................................................................................................................13
Single-in / Dual-out Mode.........................................................................................................................................13
Figure 12. Single-in / Dual-out Mode ...................................................................................................................13
Single-in / Distribution-out Mode ............................................................................................................................14
Figure 13. Single-in / Distribution-out Mode.......................................................................................................14
Single-in / DDR Dual-out Mode................................................................................................................................14
Figure 14. Single-in / DDR Dual-out Mode ..........................................................................................................14
LVDS Output Data mapping Table (6B8B = L)..........................................................................................................15
Figure 15. 8bit mode LVDS output mapping.......................................................................................................15
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TSZ02201-0L2L0H500270-1-2
06.July.2016 Rev.003