BU90R104 Datasheet, PDF (5/18 Pages) Rohm – 35bit LVDS Receiver 5:35 DeSerializer

BU90R104
Technical Note
●Pin Description
Pin Name
RA+, RA-
Pin No.
50,49
I/O
LVDS Input
Description
RB+, RB-
RC+, RC-
RD+, RD-
52,51
55,54
60,59
LVDS Input
LVDS Input
LVDS Input
LVDS data input
+ : Positive input of LVDS data differential pair.
- : Negative input of LVDS data differential pair.
RE+, RE-
62,61
LVDS Input
RCLK+, RCLK- 57,56
LVDS Input LVDS clock input
RA6～RA0
RB6～RB0
RC6～RC0
RD6～RD0
RE6～RE0
40,41,42,43,
45,46,47
32,33,34,35,
36,38,39
22,24,25,26,
27,28,29
14,15,17,18,
19,20,21
6,7,8,10,
11,12,13
Output
Output
Output LVCMOS data outputs.
Output
Output
RESERVE
2
PD
3
OE
4
R/F
VDD
5
9,23,37,48
Input
Input
Input
Input
Power
Reserved input must be “Low” for normal operation.
Power down input for the internal system.
H : Normal operation.
L : Power down (All output are “Low”).
Power down input for the data output driver.
H : Output enable (Normal operation).
L : Output disable (All outputs are “Hi-Z”).
Select input pin for data output clock triggering edge.
H : Output data is latched on rising edge.
L : Output data is latched on falling edge.
3.3V output driver and digital core power supply pin.
CLKOUT
31
Output LVCMOS level clock output.
GND
1,16,30,44
Ground GND pin for both data output driver cells and the digital cores.
LVDD
53
Power
Power supply pin for LVDS inputs.
LGND
58
Ground Ground pin for LVDS inputs.
PVDD
64
Power
Power supply pin for PLL core.
PGND
63
Ground Ground pin for PLL core.
www.rohm.com
© 2011 ROHM Co., Ltd. All rights reserved.
5/17
2011.02 - Rev.A