BU2507FV_15 Datasheet, PDF (5/21 Pages) Rohm – 10bit 4ch/6ch D/A Converters

BU2507FV BU2508FV
Timing Characteristics(Unless otherwise specified, VCC=5V, VrefH=5V, VrefL=0V, TA=25°C)
Parameter
Symbol
Limits
Min Typ Max
Conditions
Unit _{The voltage levels of the measured time}
points are 20% or 80% of VCC.
Reset L pulse width
tRTL
50
-
-
-
Clock L pulse width
tCKL
50
-
-
-
Clock H pulse width
tCKH
50
-
-
-
Clock rise time
tcr
-
-
50
-
Clock fall time
tcf
-
-
50
-
ns
Data setup time
tDCH
20
-
-
-
Data hold time
tCHD
40
-
-
-
Load setup time
tCHL
50
-
-
-
Load hold time
tLDC
50
-
-
-
Load H pulse width
D/A output settling time
tLDH
50
-
-
-
CL≤100pF^{(Note 5)}, VO: 0.5V↔4.5V
The time interval from the start time to
tLDD
-
7
20
μs change an output voltage to the time at
which the output voltage reaches to its
final value within 1/2 LSB.
(Note 5) A capacitor should be placed between the analog output and ground in order to eliminate noise.
A capacitance up to 100pF is recommended (including the capacitance of the wire).
RESET
tRTL
CLK
DI
LD
Output
tcr
tCKL
tCKH
tcf
tDCH tCHD
tCHL
tLDH
tLDC
tLDD
Applicational information
LD input
The LD input is a level trigger signal. When LD=H, an internal shift register value is loaded into a latch. It doesn’t
have to be cared whether CLK is H or L when LD changes to H. However CLK must not be changed while LD is H.
The shift register values pass through the latches if LD=H and CLK is toggled.
Power-on operation
The BU2507FV and the BU2508FV does not have a power-on reset function. Therefore, after power-on, data in
the internal registers are unknown. When RESET changes from H to L, all latch outputs turn into L, although the
shift registers are not reset.
Pull-down resister
Pin 4 is pulled up internally. If putting the external pull-down resister on it, the recommended value is less than
1kΩ.
Truth Table
Pin 4: RESET
L
Reset
H
Normal
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TSZ22111・15・001
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TSZ02201-0RLR0GZ10150-1-2
11.Dec.2015 Rev.001