BR34L02FV-W_09 Datasheet, PDF (5/18 Pages) Rohm – DDR1/DDR2 For memory module) SPD Memory

BR34L02FV-W
2.5
SPEC
2
fSCL=400kHz(VCC≧2.5V)
fSCL=100kHz(1.7V≦Vcc＜2.5V)
1.5
DATA=AA
1
Ta=25℃
Ta=85℃
0.5
Ta=-40℃
0
0
1
2
3
4
5
6
VCC[V]
Fig.10 Write Operating Current
ICC1 (fSCL=100kHz,400kHz)
0.6
0.5
0.4
fSCL=400kHz
DATA=AAh
0.3
0.2
0.1
SPEC
Ta=85℃ ^Ta=25℃
Ta=-40℃
0
0 12 3 45 6
VCC[V]
Fig.11 Read Operating Current
ICC2 (fSCL=400kHz)
Technical Note
0.6
SPEC
0.5
0.4
fSCL=100kHz
DATA=AAh
0.3
Ta=85℃
0.2
Ta=25℃
0.1
Ta=-40℃
0
0 12 3 45 6
VCC[V]
Fig.12 Read Operating Current
ICC2 (fSCL=100kHz)
2.5
SPEC
2
1.5
1
0.5
Ta=85℃
Ta=-40℃
Ta=25℃
0
0
1
2
3
4
5
6
V^VC^cC^c[[^VV^]]
Fig.13 Standby Current
ISB
10000
1000
Ta=85℃
Ta=25℃
Ta=-40℃
SPEC1
100
SPEC2
10
SPEC1:FAST-MODE
SPEC2:STANDARD-MOD
1
0
1
2
3
4
5
6
VCC[V]
Fig.14 Clock Frequency
fSCL
5
SPEC2
4
3
SPEC1:FASTE
SSSPPPEEECCC122:::FSSATTASANTN-DDMADOR-MDDEO-MDOE
2
Ta=25℃
1
SPEC1
Ta=-40℃
Ta=85℃
0
0
1
2
3
4
5
6
VCC[V]
Fig.15 Data Clock High Period
tHigh
5
SPEC2
4
3
SPEC1:FAST-MODE
SPEC2:STANDARD-MODE
2
SPEC1
1
Ta=85℃
Ta=25℃
Ta=-40℃
0
0
1
2
3
4
5
6
VCC[V]
Fig.16 Data Clock Low Period
tLow
5
SPEC2
4
3
SPEC1:FAST-MODE
SPEC2:STANDARD-MODE
2
1
SPEC1
Ta=-40℃
Ta=25℃
Ta=85℃
0
0
1
2
3
4
5
6
VCC[V]
Fig.17 Start Condition Hold Time
tHD:STA
5
SPEC2
4
3
SPEC1:FAST-MODE
SPEC2:STANDARD-MODE
2
1
SPEC1
Ta=-40℃
Ta=25℃
Ta=85℃
0
0
1
2
3
4
5
6
VCC[V]
Fig.18 Start Condition Setup Time
tSU:STA
50
0
-50
-100
SPEC1,2
Ta=85℃
Ta=25℃
Ta=-40℃
-150
SPEC1:FAST-MODE
SPEC2:STANDARD-MODE
-200
0
1
2
3
4
5
6
VCC[V]
Fig.19 Input Data Hold Time
tHD:DAT(High)
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50
0
-50
-100
SPEC1,2
SPEC1:FAST-MODE
SPEC2:STANDARD-MODE
Ta=85℃
-150
Ta=25℃
Ta=-40℃
-200
0123456
VCC[V]
Fig.20 Input Data Hold Time
tHD:DAT(LOW)
5/17
200
100
SPEC1,2
Ta=85℃
0
Ta=25℃
Ta=-40℃
-100
SPEC1:FAST-MODE
SPEC2:STANDARD-MODE
-200
0
1
2
3
4
5
6
VVCcCc[[VV]]
Fig.21 Input Data Setup Time
tSU:DAT(High)
2009.04 - Rev.A