BU9409FV_12 Datasheet, PDF (45/58 Pages) Rohm – 32bit Audio DSP

BU9409FV
Technical Note
8. Command sent after releasing reset
Please send the following command after releasing reset including power supply on.
0. Power supply turning on
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○ Please input the clock from the outside. When the clock is not input, reset can't normally be done.
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1. Reset release (RESETB="H")
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2. &hA0[7:0] = C2h ：Set PLLA.
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3. &hF3[5:0] = 10h ：Set the dividing frequency ratio of MCLK. Please do as follows to set a value by fs of
MCLK.
（MCLK:512fs=10h、256fs=08h、128fs=04h）
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4. &hF5[3:0] = 1h：Set the dividing frequency ratio of PLL.
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5. &hF6[5:0] = 23h：Set the phase match of PLL.
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6. &hF1[4] = 0 ：Turn on the analog input.
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7. &h08[5:4] = 1h ：Select the system clock.
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8. &hA7[7:0] = F4h：Synchronous detection condition setting 1 for PLLA is initialized.
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9. &hA8[7:0] = 33h：Synchronous detection condition setting 2 for PLLA is initialized.
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10. &hA9[3:0] = 3h：Synchronous detection condition setting 3 for PLLA is initialized.
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11. &hA9[5:4] = 2h or 1h or 0h ：Set MCLK.
(Set in “2h”While MCLK is 512fs, set in “1h”While MCLK is 256fs, set in “0h”While MCLK is 128fs.)
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○ It is about 20ms weight until PLL is steady.
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10. &h01[5:4] = 0h ：Turn off the RAM Clear.
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11. Other register setting
&h26[7:0] = **h ：Release the mute of the Main output volume（30h=0dB）.
&h2C[7:0] = **h ：Release the mute of the Sub output volume（30h=0dB）.
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2012.03 - Rev.A