BU9409FV_12 Datasheet, PDF (11/58 Pages) Rohm – 32bit Audio DSP

BU9409FV
Technical Note
2-4. Output data selection(SEL2) to P-S conversion2 (SDATAO2 Terminal)
Default = 0
Select Address
&h04 [ 5：4 ]
Value
0
1
2
3
Operating Description
Sub data output after DSP is processed.
Main data output after DSP is processed.
Sub data output before DSP is processed.
Main data output before DSP is processed.
2-5. SPDIFO Terminal output data selection（SEL2）
Default = 0
Select Address
&h05 [ 1：0 ]
Value
0
1
2
3
Operating Description
Main data output after DSP is processed.
Sub data output after DSP is processed.
Main data output before DSP is processed.
Sub data output before DSP is processed.
2-6. System clock selection（SEL3）
Select the DSP clock supplied to S-P conversion1、S-P conversion2、DSP、P-S conversion1、P-S conversion2、S/PDIF
output part.
Default = 0
Select Address
&h08 [ 5：4 ]
Value
0
Operating Description
Chose the input from a MCLK terminal as a clock.
1
Chose the PLL output as a clock.
2
Chose the input from a SDATA2terminal as a clock. (used for IC test).
3
After power on or reset released, system block selection uses clock(even if not 512fs is ok) input from terminal MCLK to
receive I2C command and initialize BU9409. Then set the dividing frequency ratio of PLL block (mclk_div, pll_div) that is
suitable for the clock frequency from terminal MCLK , when PLL_512fs clock from PLL is steady, set &h08 = 10h.
2-7. Dividing frequency ratio setting of PLL block which corresponding to input clock from terminal MCLK
Sampling rate of input clock
Setting of mclk_div
Setting of pll_div
PLL initialization
&hF3
&hF5
&hF6
512fs（24.576MHz、fs=48kHz）
10h
01h
23h
256fs（12.288MHz、fs=48kHz）
08h
01h
23h
128fs（6.144MHz、fs=48kHz）
04h
01h
23h
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2012.03 - Rev.A