BU2396KN_15 Datasheet, PDF (4/24 Pages) Rohm – 3ch Clock Generator for Digital Cameras

BU2396KN
Electrical Characteristics
(VDD=3.3V, Ta=25°C, Crystal =12.000000MHz, unless otherwise specified.)
Parameter
Symbol
Limit
Min
Typ
Max
Operating Circuit
Current
IDD
－
23
35
【Output H Voltage】
TGCLK
VOHT
VDD-0.5
－
－
VCLK
VOHV
VDD-0.5
－
－
UCLK
VOHU
VDD-0.5
－
－
【Output L Voltage】
TGCLK
VOLT
－
－
0.5
VCLK
VOLV
－
－
0.5
UCLK
VOLU
－
－
0.5
【Pull-Up Resistance Value】
Unit
Conditions
mA At no load
V When current load =-5.0mA
V When current load =-5.0mA
V When current load =-5.0mA
V When current load =5.0mA
V When current load =5.0mA
V When current load =5.0mA
TGCLK_SEL1
TGCLK_SEL2
Pull-up
R
125
250
375
KΩ Monitor pin = 0V (R=VDD/I)
【Pull-Down Resistance Value】
TGCLK_EN,
TGCLK_PD
VCLK_EN, VCLK_PD
Pull-down
R
25
50
75
KΩ Monitor pin = VDD (R=VDD/I)
【Output Frequency】
TGCLK
SEL2:L
TGCLK
SEL2:H
SEL1:L
SEL1:L
TGCLK1
TGCLK2
24.000000
30.000000
MHz XTAL x (48/4)/6
MHz XTAL x (60/4)/6
TGCLK SEL1:H
TGCLK3
36.000000
MHz XTAL x (54/3)/6
VCLK
VCLK
27.000000
MHz XTAL x (54/3)/8
UCLK
UCLK
12.000000
MHz XTAL output
【Output waveform】
Duty
Rise Time
Fall Time
Duty
45
50
55
%
Measured at a voltage of 1/2 of
VDD
Period of transition time
tR
2.0
nsec required for the output to reach
80% from 20% of VDD.
Period of transition time
tF
2.0
nsec required for the output to reach
20% from 80% of VDD.
【Jitter】
Period-Jitter 1σ
P-J1σ
50
psec ^{(Note 1)}
Period-Jitter MIN-MAX
P-J
MIN-MAX
300
psec ^{(Note 2)}
【Output Lock-Time】
tLOCK
1
msec ^{(Note 3)}
(Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to XTALIN.
If the input frequency is set to 12.000000MHz, the output frequency will be as listed above.
(Note 1) Period-Jitter 1σ
This parameter represents standard deviation (=1σ) on cycle distribution data at the time when the output clock cycles are sampled 1000 times consecutively
with the TDS7104 Digital Phosphor Oscilloscope of Tektronix Japan, Ltd.
(Note 2) Period-Jitter MIN-MAX
This parameter represents a maximum distribution width on cycle distribution data at the time when the output clock cycles are sampled 1000 times
consecutively with the TDS7104 Digital Phosphor Oscilloscope of Tektronix Japan, Ltd.
(Note 3) Output Lock-Time
The Lock-Time represents elapsed time after power supply turns ON to reach a 3.0V voltage, after the system is switched from Power-Down state to normal
operation state, or after the output frequency is switched, until it is stabilized at a specified frequency, respectively.
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TSZ22111・15・001
4/20
TSZ02201-0E3E0J500710-1-2
04.Nov.2015 Rev.001