BU2396KN_15 Datasheet, PDF (2/24 Pages) Rohm – 3ch Clock Generator for Digital Cameras

BU2396KN
Block Diagram and Pin Configuration
XIN 4
XOUT 5
XTAL
OSC
TGCLK_EN 10
TGCLK_SEL2 7
TGCLK_SEL1 8
TGCLK_PD 9
VCLK_PD ²⁰
VCLK_EN 12
TOP VIEW
12.000000MHz
16 ^UCLK
DATA
PLL1
30.000000MHz
24.000000MHz
36.000000MHz
1／6
11 TGCLK
PLL2
1／8
27.000000MHz
19 ^VCLK
Pin Descriptions
Pin No.
Pin Name
Function
1
AVDD
Analog power source
2
AVDD
Analog power source
3
AVSS
Analog GND
4
XIN
Crystal IN
5
XOUT
Crystal OUT
6
TEST
TEST pin, normally open, equipped with pull-down
7
TGCLK_SEL2 TGCLK frequency selection, equipped with pull-up
8
TGCLK_SEL1 TGCLK frequency selection, equipped with pull-up
9
TGCLK_PD
TGCLK Power-Down control, H:enable, L:Power-Down, equipped with pull-down
10
TGCLK_EN
TGCLK output control, H: Enable, L: Output fixed to L, equipped with pull-down
11
TGCLK
36M, 30M, 24M output
12
VCLK_EN
VCLK output control, H:enable, L: Output fixed to L, equipped with pull-down
13
VSS1
TGCLK,UCLK & Internal digital GND
14
VDD1
TGCLK,UCLK & Internal digital power supply
15
VDD1
TGCLK,UCLK & Internal digital power supply
16
UCLK
12M output
17
VSS2
VCLK GND
18
VDD2
VCLK power source
19
VCLK
27M output
20
VCLK_PD
VCLK Power-Down control, H:enable, L:Power-Down, equipped with pull-down
(Note) Basically, mount ICs to the printed circuit board for use.
If the ICs are not mounted to the printed circuit board, the characteristics of ICs may not be fully demonstrated.
Mount 0.1µF as bypass capacitors near IC pins between PIN 1&2 and PIN 3, PIN 13 and PIN 14&15, and PIN 17 and PIN 18 respectively.
As to the jitters, the TYP values vary with the substrate, power supply, output loads, noises, and others. Also, the operating margin should be thoroughly
checked.
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TSZ22111・15・001
2/20
TSZ02201-0E3E0J500710-1-2
04.Nov.2015 Rev.001