BD9533EKN_08 Datasheet, PDF (4/21 Pages) Rohm – Switching Regulators for DDR-SDRAM Cores

●Reference Data
600
590
580
570
560
550
-10 10 30 50 70 90
Ta(℃)
Fig.1 Ta vs Icc
4.30
4.25
Sweep up
4.20
4.15
4.10
Sweep down
4.05
4.00
-10 10 30 50 70 90
Ta(℃)
Fig.4 Ta vs UVLO (VIN)
2.8
2.4
2.0
1.6
1.2
Right: -10℃
0.8
Middle: 25℃
Left: 100℃
0.4
0.0
0
1.5
3
4.5
6
Vcc(V)
Fig.7 VCC vs VREG (Start up)
400
350
300
250
200
Top: -10℃
Middle: 25℃
150
Bottom: 100℃
100
50
0
0.6 0.8 1 1.2 1.4 1.6 1.8 2
REF [V]
Fig.10 REF-ON TIME
(VIN=25V)
2.500
2.498
2.496
2.494
2.492
2.490
-10
10 30 50 70 90
Ta(℃)
Fig.2 Ta vs VREG
2.20
2.15
2.10
Sweep up
2.05
2.00
1.95
Sweep down
1.90
-10 10 30 50 70 90
Ta(℃)
Fig.5 Ta vs UVLO (VREG)
1000
900
800
700
600
Top: -10℃
500
Middle: 25℃
400
Bottom: 100℃
300
200
100
0
0.6 0.8 1 1.2 1.4 1.6 1.8 2
REF [V]
Fig.8 REF vs ON TIME
(VIN=7V)
1200
1000
800
Top: -10℃
Middle: 25℃
600
Bottom: 100℃
400
200
0
5
10
15
20
25
VIN [V]
Fig.11 VIN-ON TIME
(REF=1.8V)
4.30
4.25
Sweep up
4.20
4.15
4.10
Sweep down
4.05
4.00
-10 10 30 50 70 90
Ta(℃)
Fig.3 Ta vs UVLO (VCC)
1.7
1.6
Sweep up
1.5
1.4
Sweep down
1.3
1.2
-10 10 30 50 70 90
Ta(℃)
Fig.6 Ta vs EN Threshold
600
500
400
300
200
Top: -10℃
Middle: 25℃
100
Bottom: 100℃
0
0.6 0.8 1 1.2 1.4 1.6 1.8 2
REF [V]
Fig.9 REF vs ON TIME
(VIN=12V)
3
2
1
0
-1
-2
-3
-10 10 30 50 70 90
Ta [℃]
Fig.12 Ta vs VOUT offset
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