BD9533EKN_08 Datasheet, PDF (19/21 Pages) Rohm – Switching Regulators for DDR-SDRAM Cores

11. Regarding input pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.
P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode
or transistor. For example, the relation between each potential is as follows:
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes can occur inevitable in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes
operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should not be used.
Pin A
N
N ^P+
Parasitic element
Resistor
Pin A
P
P⁺ _N
P substrate
GND
Transistor (NPN)
Pin B _C B
Pin B
E
Parasitic
element
N _P+
Parasitic element
N
P
P⁺ _N
P substrate
GND
GND
B
C
E
Parasitic
element
GND
Other adjacent elements
Fig. 37 Example of IC structure
12. Ground Wiring Pattern
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns,
placing a single ground point at the ground potential of application so that the pattern wiring resistance and voltage
variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the
GND wiring pattern of any external components, either.
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