BU7485G-TR Datasheet, PDF (31/43 Pages) Rohm – Ground Sense High Speed Low Voltage CMOS Operational Amplifiers

BU7485G BU7485SG BU7486xxx BU7486Sxxx BU7487xx BU7487Sxx ^Datasheet
Operational Notes
1) Unused circuits
When there are unused circuits, it is recommended that they are
connected as in Figure .56, setting the non-inverting input terminal to a
potential within the in-phase input voltage range (Vicm).
2) Input voltage
Applying VSS-0.3V to VDD+0.3V to the input terminal is possible
without causing deterioration of the electrical characteristics or
destruction, regardless of the supply voltage. However, this does not
ensure normal circuit operation. Please note that the circuit operates
normally only when the input voltage is within the common mode input
voltage range of the electric characteristics.
3) Power supply (single / dual)
The op-amp operates when the voltage supplied is between VDD and
VSS. Therefore, the single supply op-amp can be used as dual supply
op-amp as well.
Connect
to Vicm
VDD
Vicm
VSS
Figure 80. Example of application
circuit for unused op-amp
4) Power Dissipation (Pd)
Using the unit in excess of the rated power dissipation may cause deterioration in electrical characteristics including
reduced current capability due to the rise of chip temperature. Therefore, please take into consideration the power
dissipation (Pd) under actual operating conditions and apply a sufficient margin in thermal design. Refer to the thermal
derating curves for more information.
5) Short-circuit between pins and erroneous mounting
Be careful when mounting the IC on printed circuit boards. The IC may be damaged if it is mounted in a wrong orientation
or if pins are shorted together. Short circuit may be caused by conductive particles caught between the pins.
6) Operation in a strong electromagnetic field
Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.
7) IC handling
Applying mechanical stress to the IC by deflecting or bending the board may cause fluctuations of the electrical
characteristics due to piezo resistance effects.
8) Board Inspection
Connecting a capacitor to a pin with low impedance may stress the IC. Therefore, discharging the capacitor after every
process is recommended. In addition, when attaching and detaching the jig during the inspection phase, make sure that
the power is turned OFF before inspection and removal. Furthermore, please take measures against ESD in the
assembly process as well as during transportation and storage.
9) Output capacitor
If a large capacitor is connected between the output pin and VSS pin, current from the charged capacitor will flow into the
output pin and may destroy the IC when the VCC pin is shorted to ground or pulled down to 0V. Use a capacitor smaller
than 0.1uF between output pin and VSS pin.
10) Oscillation by output capacitor
Please pay attention to the oscillation by output capacitor and in designing an application of negative feedback loop
circuit with these ICs.
11) Latch up
Be careful of input voltage that exceed the VDD and VSS. When CMOS device have sometimes occur latch up and
protect the IC from abnormaly noise.
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TSZ02201-0RAR1G200380-1-2
12.JUL.2013 Rev.001