BU99022NUX-3 Datasheet, PDF (3/26 Pages) Rohm – I2C BUS 2kbit + 2kbit 2ports serial EEPROM

BU99022NUX-3
●AC operating characteristic
(Unless otherwise specified, Ta=－40～+85℃, VCC=1.7～5.5V)
Parameter
Limit
Symbol
Unit
Min.
Typ.
Max.
SCL frequency
fSCL
－
－
400
kHz
Data clock “HIGH“ time
tHIGH
0.6
－
－
μs
Data clock “LOW“ time
SDA, SCL rise time ^*1*2
SDA, SCL fall time ^*1*2
tLOW
1.2
－
－
μs
tR
－
－
1.0
μs
tF
－
－
1.0
μs
Start condition hold time
tHD:STA
0.6
－
－
μs
Start condition setup time
tSU:STA
0.6
－
－
μs
Input data hold time
tHD:DAT
0
－
－
ns
Input data setup time
tSU:DAT
100
－
－
ns
Output data delay time
tPD
0.1
－
0.9
μs
Output data hold time
tDH
0.1
－
－
μs
Stop condition setup time
tSU:STO
0.6
－
－
μs
Bus release time before
transfer start
tBUF
1.2
－
－
μs
Internal write cycle time
tWR
－
－
5
ms
Noise removal valid period
(SDA, SCL terminal)
tI
－
－
0.1
μs
WP hold time
tHD:WP
1.0
－
－
μs
WP setup time
tSU:WP
0.1
－
－
μs
WP valid time
tHIGH:WP
1.0
－
－
μs
*1 Not 100% TESTED.
*2 It is recommended that tR/tF is less than 300ns fundamentally.
When tR/tF is more than 300ns and less than 1us, it is possible that other device on the
same bus are entered unintended start/stop condition. For prevent it, note in designing
the AC timing.
Condition
Input data level:VIL=0.2×Vcc VIH=0.8×Vcc
Input data timing refarence level: 0.3×Vcc/0.7×Vcc
Output data timing refarence level: 0.3×Vcc/0.7×Vcc
Rise/Fall time : ≦20ns
●Sync data input / output timing
SCL
70%
70%
SDA
(input)
tBUF
SDA
(output)
tR
tF
tHIGH
70% 70%
30%
30%
tLOW
tSU:DAT
70%
70%
30%
tPD
70%
30%
tHD:DAT
70%
30%
tDH
70%
30%
70%
30%
○Input read at the rise edge of SCL
○Data output in sync with the fall of SCL
Fig.1-(a) Sync data input / output timing
70%
DATA(1)
D1
D0 ACK
DATA(n)
ACK
70%
tWR
30%
30%
tSU:WP
tHD:WP
STOP CONDITION
Fig.2 WP timing at write execution
70%
70%
70%
tSU:STA
tHD:STA
tSU:STO
70%
30%
30%
START CONDITION
Fig.1-(b) Start-stop bit timing
STOP CONDITION
DATA(1)
D1 D0 ACK
DATA(n)
tHIGH:WP
70%
70%
ACK
70%
tWR
Fig.3 WP timing at write cancel
Datasheet
D0
write data
(n-th address)
ACK
70%
70%
tWR
STOP CONDITION START CONDITION
Fig.1-(c) Write cycle timing
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TSZ22111・14・001
3/23
TSZ02201-0R2R0G100010-1-2
2011.12.19 Rev.001