BU99022NUX-3 Datasheet, PDF (17/26 Pages) Rohm – I2C BUS 2kbit + 2kbit 2ports serial EEPROM

BU99022NUX-3
Datasheet
●WP valid timing (write cancel)
WP2 is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP valid timing.
During write cycle execution, in cancel valid area, by setting WP2='H', write cycle can be cancelled. In both byte write cycle and page write
cycle, the area from the first start condition of command to the rise of clock to taken in D0 of data(in page write cycle, the first byte data) is
cancel invalid area.
WP input in this area becomes Don't care. The area from the rise of SCL to take in D0 to input the stop condition is cancel valid area. And,
after execution of forced end by WP, standby status gets in.
・Rise of D0 taken clock
SCL
SDA
D1 D0 ACK
Enlarged view
・Rise of SDA
SCL
SDA D0 ACK
Enlarged view
SDA
S
T _Slave
A
R ^address
T
A
C ^Word
K
L
address
A
C
K
L
A
D7 D6 D5 D4 D3 D2 D1 D0 _C
K
L
Data
AS
CT
KO
LP
tWR
WP2
WP cancel invalid area
WP cancel valid area WP cancel invalid area
Data is not written.
Fig.50 WP valid timing
●Command cancel by start condition and stop condition
During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Fig.51)
However, in ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and stop condition cannot be
input, so reset is not available. Therefore, execute software reset. And when command is cancelled by start, stop condition, during random
read cycle, sequential read cycle, or current read cycle, internal setting address is not determined, therefore, it is not possible to carry out
current read cycle in succession. When to carry out read cycle in succession, carry out random read cycle.
SCL
SDA
1
0
1
0
Start condition Stop condition
Fig.51 Case of cancel by start, stop condition during slave address input
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TSZ22111・14・001
17/23
TSZ02201-0R2R0G100010-1-2
2011.12.19 Rev.001