BU9897GUL-W_11 Datasheet, PDF (3/17 Pages) Rohm – High Reliability Series Serial EEPROMs WL-CSP EEPROM family I2C BUS

BU9897GUL-W
●Sync data input/output timing
SCL
SDA
(Input)
SDA
(Output)
tHD :STA
tBUF
tR
tF
tHIGH
tSU :DAT tLOW
tHD :DAT
tPD
tDH
○Input read at the rise edge of SCL
○Data output in sync with the fall of SCL
Fig.1-(a) Sync data input / output timing
SCL
tSU :STA
SDA
tHD :STA
tSU :STO
START BIT
Fig.1-(b) Start - stop bit timing
STOP BIT
SCL
SDA
D0 ACK
WRITE DATA(n)
tWR
STOP
START
CONDITION CONDITION
Fig.1-(c) Write cycle timing
Technical Note
SCL
SDA
DATA(1)
D1 D0
ACK
WP
tSU：WP
DATA(n)
ACK
tWR
Stop condition
tHD：WP
Fig.1-(d) WP timing at write execution
SCL
SDA
WP
DATA(1)
D1 D0 ACK
DATA(n)
tHIGH:WP
ACK
tWR
○At write execution, in the area from the D0 taken clock rise
of the first DATA(1), to tWR, set WP= 'LOW'.
○By setting WP "HIGH" in the area, write can be cancelled.
When it is set WP = 'HIGH' during tWR, write is forcibly ended,
and data of address under access is not guaranteed, therefore write it
once again.
Fig.1-(e) WP timing at write cancel
●Block diagram
A0 1
A1 2
14bit
128Kbit EEPROM array
Adddress
decoder
14bit
Slave - word
address register
8bit
Data
register
A2 3
GND 4
START
Control circuit
STOP
ACK
High voltage
generating circuit
Power source
voltage detection
Fig.2 Block diagram
8 Vcc
7 WP
6 SCL
5 SDA
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3/16
2011.10 - Rev.A