BU9889GUL-W_12 Datasheet, PDF (3/27 Pages) Rohm – WLCSP EEPROM

BU9889GUL-W (8Kbit)
Datasheet
●Sync Data Input / Output Timing
SCL
SDA
(In(p入ut)力 )
SDA
(O(u出tpu力t) )
tHD:STA
tBUF
tR
tF tHIGH
tSU:DAT tLOW
tPD
tHD:DAT
tDH
○Input read at the rise edge of SCL
○Data output in sync with the fall of SCL
SCL
SDA
DATA(1)
D1 D0 ACK
WP
tSU：WP
DATA(n)
ACK
ｔWR
Stスopトッcoプnコdンitioデnィション
ｔHD：WP
Figure 1-(a) Sync data input / output timing
Figure 1-(d) WP timing at write execution
SCL
tSU:STA
SDA
tHD:STA
tSU:STO
START BIT
STOP BIT
Figure 1-(b) Start - stop bit timing
SCL
SDA
DATA(1)
D1 D0 ACK
DATA(n)
tHIGH:WP
WP
ACK
tWR
○At write execution, in the area from the D0 taken clock rise of the first DATA(1),
to tWR, set WP= 'LOW'.
○By setting WP "HIGH" in the area, write can be cancelled.
When it is set WP = 'HIGH' during tWR, write is forcibly ended, and data of address under
access is not guaranteed, therefore write it once again.
Figure 1-(e) WP timing at write cancel
SCL
SDA
D0
WRITE DATA(n)
ACK
tWR
STOP
CONDITION
START
CONDITION
Figure 1-(c) Write cycle timing
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TSZ22111・15・001
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TSZ02201-0R2R0G100490-1-2
05.SEP.2012 Rev.001