BU9889GUL-W_12 Datasheet, PDF (12/27 Pages) Rohm – WLCSP EEPROM

BU9889GUL-W (8Kbit)
Datasheet
●I²C BUS communication
○I²C BUS data communication
I²C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long,
and acknowledge is always required after each byte.
I²C BUS carries out data transmission with plural devices connected by 2 communication lines of serial data (SDA) and
serial clock (SCL).
Among devices, there are “master” that generates clock and control communication start and end, and “slave” that is
controlled by addresses peculiar to devices.
EEPROM becomes “slave”. And the device that outputs data to bus during data communication is called “transmitter”,
and the device that receives data is called “receiver”.
SDA
1-7
8
9
1-7
8
9
1-7
8
SCL
S
START ADDRESS R/W ACK
DATA
ACK
DATA
condition
Figure 30. Data transfer timing
9
P
ACK STOP
condition
○Start condition (start bit recognition)
・Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is
'HIGH' is necessary.
・This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this condition is
satisfied, any command is executed.
○Stop condition (stop bit recognition)
・Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH'
○Acknowledge (ACK) signal
・This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In master
and slave, the device (µ-COM at slave address input of write command, read command, and this IC at data output of
read command) at the transmitter (sending) side releases the bus after output of 8bit data.
・The device (this IC at slave address input of write command, read command, and µ-COM at data output of read
command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK
signal) showing that it has received the 8bit data.
・This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'.
・Each write action outputs acknowledge signal) (ACK signal) 'LOW', at receiving 8bit data (word address and write data).
・Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'.
・When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (µ-COM) side, this IC
continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and recognizes
stop condition (stop bit), and ends read action. And this IC gets in standby status.
○Device addressing
・Following a START condition, the master output the slave address to be accessed.
・The most significant four bits of the slave address are the “device type indentifier,” for this device it is fixed as “1010”.
・The next bit (device address) identify the specified device on the bus. The device address is defined by the state of A2
input pin. This IC works only when the device address inputted from SDA pin correspond to the state of A2 input pin.
Using this address scheme, up to two devices may be connected to the bus.
・The next two bits (P1, P0) are used by the master to select four 256 word page of memory.
P1, P0 set to “0” “0” ･･･ 1page (000 to 0FF)
P1, P0 set to “0” “1” ･･･ 1page (100 to 1FF)
P1, P0 set to “1” “0” ･･･ 1page (200 to 2FF)
P1, P0 set to “1” “1” ･･･ 1page (300 to 3FF)
・The last bit of the stream (R/W … READ/WRITE) determines the operation to be performed. When set to “1”, a read
operation is selected ; when set to “0”, a write operation is selected.
R/W set to “0” ･･･ WRITE (including word address input of Random Read)
R/W set to “1” ･･･ READ
1010
A2
P1
P0
―
R/W
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TSZ22111・15・001
12/23
TSZ02201-0R2R0G100490-1-2
05.SEP.2012 Rev.001