BU9880GUL-W_12 Datasheet, PDF (3/26 Pages) Rohm – WLCSP EEPROM

BU9880GUL-W (64Kbit)
●Sync Data Input / Output Timing
SCL
SDA
(Input)
SDA
(Output)
tHD :STA
tBUF
tR
tF
tHIGH
tSU :DAT tLOW
tPD
tHD :DAT
tDH
○Input read at the rise edge of SCL
○Data output in sync with the fall of SCL
Figure 1-(a) Sync data input / output timing
Datasheet
SCL
SDA
DATA(1)
D1 D0 ACK
WP
tSU：WP
DATA(n)
ACK
tWR
Stop condition
tHD：WP
Figure 1-(d) WP timing at write execution
SCL
tSU :STA
SDA
tHD :STA
tSU :STO
START BIT
STOP BIT
Figure 1-(b) Start - stop bit timing
SCL
SDA
D0 ACK
WRITE DATA(n)
tWR
STOP
START
CONDITION CONDITION
Figure 1-(c) Write cycle timing
SCL
SDA
DATA(1)
D1 D0 ACK
DATA(n)
tHIGH:WP
WP
ACK
tWR
○At write execution, in the area from the D0 taken clock rise
of the first DATA(1), to tWR, set WP= 'LOW'.
○By setting WP "HIGH" in the area, write can be cancelled.
When it is set WP = 'HIGH' during tWR, write is forcibly ended,
and data of address under access is not guaranteed, therefore write it
once again.
Figure 1-(e) WP timing at write cancel
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TSZ22111・15・001
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TSZ02201-0R2R0G100340-1-2
21.AUG.2012 Rev.001