BU9847GUL-W_12 Datasheet, PDF (3/28 Pages) Rohm – WLCSP EEPROM

BU9847GUL-W (4Kbit)
●Sync Data Input / Output Timing
tR
tF
tHIGH
SCL
tHD:STA
tSU:DAT
tLOW
SDA
(Input)
tBUF
tPD
SDA
(Output)
○Input read at the rise edge of SCL
○Data output in sync with the fall of SCL
tHD:DAT
tDH
Figure 1-(a) Sync data input / output timing
Datasheet
SCL
SDA
DATA(1)
D1 D0 ACK
WP
DATA(n)
ACK
ｔWR
sスtトoッpプcコoンnデdィiシtioョンn
tSU：WP
ｔHD：WP
Figure 1-(d) WP timing at write execution
SCL
tSU:STA
SDA
tHD:STA
tSU:STO
START BIT
STOP BIT
Figure 1-(b) Start – stop bit timing
SCL
SDA
D0
ACK
Write data
（ｎ-th address）
Stop condition
tWR
Start condition
Figure 1-(c) Write cycle timing
SCL
SDA
DATA(1)
D1 D0 ACK
DATA(n)
tHIGH:WP
WP
ACK
tWR
Figure 1-(e) WP timing at write cancel
○At write execution, in the area from the DO taken clock rise of the first DATA (1),
to tWR, set WP=”LOW”
○By setting WP “HIGH” in the area, write can be cancelled.
When it is set WP=”HIGH” during tWR, write is forcibly ended, and data of
address under access is not guaranteed, therefore write it once again.
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
3/24
TSZ02201-0R2R0G100480-1-2
4.SEP.2012 Rev.001