BU9844GUL-W_13 Datasheet, PDF (3/30 Pages) Rohm – WLCSP EEPROM

BU9844GUL-W (16Kbit)
Datasheet
Action timing characteristics (Unless otherwise specified, Ta=-40°C to +85°C, V_CC =1.7V to 5.5V)
FAST-MODE
STANDARD-MODE
Parameter
Symbol
2.5V≤V_CC≤5.5V
1.7V≤V_CC≤5.5V
Unit
Min. Typ. Max. Min. Typ. Max.
SCL Frequency
f_SCL
-
-
400
-
-
100 kHz
Data Clock “HIGH” Time
t_HIGH
0.6
-
-
4.0
-
-
μs
Data Clock “LOW” Time
SDA, SCL Rise Time ^(Note1)
SDA< SCL Fall Time ^(Note1)
t_LOW
1.2
-
-
4.7
-
-
μs
t_R
-
-
0.3
-
-
1.0
μs
t_F
-
-
0.3
-
-
0.3
μs
Start Condition Hold Time
t_HD:STA
0.6
-
-
4.0
-
-
μs
Start Condition Setup Time
t_SU:STA
0.6
-
-
4.7
-
-
μs
Input Data Hold Time
t_HD:DAT
0
-
-
0
-
-
ns
Input Data Setup Time
t_SU:DAT
100
-
-
250
-
-
ns
Output Data Delay Time
t_PD
0.1
-
0.9 0.2
-
3.5
μs
Output Data Hold Time
t_DH
0.1
-
-
0.2
-
-
μs
Stop Condition Setup Time
t_SU:STO
0.6
-
-
4.7
-
-
μs
Bus Release Time Before Transfer Start
t_BUF
1.2
-
-
4.7
-
-
μs
Internal Write Cycle Time
t_WR
-
-
5
-
-
5
ms
Noise Removal Valid Period (SDA, SCL terminal)
t_I
-
-
0.1
-
-
0.1
μs
WP Hold Time
t_HD:WP
0
-
-
0
-
-
ns
WP Setup Time
t_SU:WP
0.1
-
-
0.1
-
-
μs
WP Valid Time
(Note1) Not 100% tested.
t_HIGH:WP
1.0
-
-
1.0
-
-
μs
Sync Data Input / Output Timing
tR
tF
tHIGH
SCL
tHD:STA
tSU:DAT
tLOW
SDA
(Input)
tBUF
tPD
SDA
(Output)
○Input read at the rise edge of SCL
○Data output in sync with the fall of SCL
tHD:DAT
tDH
Figure 1-(a) Sync data input / output timing
SCL
DATA(1)
SDA D1 D0 ACK
WP
DATA(n)
ACK
ｔWR
stop condition
tSU：WP
ｔHD：WP
Figure 1-(d) WP timing at write execution
SCL
tSU:STA
tHD:STA
SDA
tSU :STO
START BIT
STOP BIT
Figure 1-(b) Start – stop bit timing
SCL
SDA
D0
Write data
(n-th address)
ACK
Stop condition
tWR
Start condition
Figure 1-(c) Write cycle timing
SCL
DATA(1)
DATA(n)
SDA D1 D0 ACK
tHIGH:WP
WP
ACK
tWR
Figure 1-(e) WP timing at write cancel
○At write execution, in the area from the DO taken clock rise of the first DATA (1),
to tWR, set WP=”LOW”
○By setting WP “HIGH” in the area, write can be cancelled.
When it is set WP=”HIGH” during tWR, write is forcibly ended, and data of
address under access is not guaranteed, therefore write it once again.
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TSZ02201-0R2R0G100470-1-2
17.Sep.2013 Rev.002