BU24026GU_11 Datasheet, PDF (3/8 Pages) Rohm – Silicon monolithic integrated circuit

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◇3-wire serial interface
Control commands are framed by 16-bit serial input (MSB first) and input through the CSB, SCLK, and SDATA pins.
4 higher-order bits specify addresses, while the remaining 12 bits specify data.
Data of every bit is input through the SDATA pin, retrieved on the rising edges of SCLK.
Data becomes valid in the CSB Low area. The loading timing is different in the resistor. (as shown in “Note 5,6”)
Furthermore, the interface will be synchronized with the falling edges of SCLK to output the SOUT data of the 12 bits.
CSB
SCLK
SDATA ^{x D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0}
x
SOUT
Hiz
Address
x
Data
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hiz
<Register map>
Address[3:0]
15
14
13
12
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
Addresses other than those above
11
10
ModeA[1:0]
0
0
0
0
1
1
EnA RtA
Ach status[1:0]
ModeB[1:0]
0
0
0
0
1
1
EnB RtB
Bch status[1:0]
ModeC[1:0]
0
0
0
0
1
0
1
1
1
1
EnC RtC
Cch status[1:0]
0
0
0
0
0
0
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
0
0
0
1
1
0
1
0
1
0
1
1
Data[11:0]
9
8
7
6
5
4
3
2
1
0
SelA[1:0]
0
Ach different output voltage[6:0]
0
0
Ach Cycle[7:0]
1
0
Ach Cycle[15:8]
1
0
0
0
APOS[1:0]
0
0
0 ASTOP
Ach Pulse[9:0]
Ach operation pulse number[9:0]
SelB[1:0]
0
Bch different output voltage [6:0]
0
0
Bch Cycle[7:0]
1
0
Bch Cycle[15:8]
1
0
0
0
BPOS[1:0]
0
0
0 BSTOP
Bch Pulse[9:0]
Bch operation pulse number[9:0]
SelC[1:0]
0
Cch different output voltage [6:0]
0
0
Cch Cycle[7:0]
1
0
Cch Cycle[15:8]
1
5_PWM_Ct[1:0]
5ch different output voltage[6:0]
0
6_PWM_Ct[1:0]
6ch different output voltage[6:0]
1
0
0
0
CPOS[1:0]
0
0
0 CSTOP
Cch Pulse[9:0]
Cch operation pulse number[9:0]
Chopping[1:0] CacheM
SEL56[2:0]
P_CTRL
CLK_DIV[2:0]
0
0
0
0
0
0
0
0
PI_CTRL1 PI_CTRL2
1
0
0
5_PULSE_CNT 5_PULSE_BASE[1:0]
0
6_PULSE_CNT 6_PULSE_BASE[1:0]
0
0
5_PULSE_COUNT[7:0]
0
1
6_PULSE_COUNT[7:0]
1
0
0 EXT_EN 0 EXT_RT
EXT_NUM[3:0]
0
0
EXT_PAT1
EXT_PAT0
0
1
EXT_PAT3
EXT_PAT2
1
0
EXT_PAT5
EXT_PAT4
1
1
EXT_PAT7
EXT_PAT6
0
0
EXT_PAT9
EXT_PAT8
0
1
EXT_PAT11
EXT_PAT10
1
0
EXT_PAT13
EXT_PAT12
1
1
EXT_PAT15
EXT_PAT14
0
0
Constant current driver reference voltage adjustment 8bit DAC[7:0]
0
0
0
0
0
0
0
0
7_CTRL[1:0]
0
0
0
0
Wavefoming circuit 1 Vthh[5:0]
0
1
0
0
Wavefoming circuit 1 Vthl[5:0]
1
0
0
0
0
0
0
0
HYS3
HYS2
0
0
0
0
0
0
0
0
0
CMD_RS
Setting prohibited
(Note 1) The notations A, B, C in the register map correspond to Ach, Bch and Cch respectively.
(Note 2) The Ach is defined as 1ch and 2ch driver output, the Bch as 3ch and 4ch driver output, and Cch as 5ch and 6ch driver output.
(Note 3) After resetting (Power ON reset, and CMD_RS), “initial setting” is saved in all registers.
REV. B