BU2394KN_08 Datasheet, PDF (3/17 Pages) Rohm – 3ch Clock Generator for Digital Cameras

BU2396N(VDD=3.3V, Ta=25℃, Crystal =12.000000MHz, unless otherwise specified.)
Parameter
Symbol
Min.
【Action circuit current】
IDD
－
Limit
Typ.
23
Max.
35
Unit
Condition
mA At no load
【Output H voltage】
TGCLK
VOHT
VDD-0.5
－
－
V When current load =-5.0mA
VCLK
VOHV
VDD-0.5
－
－
V When current load =-5.0mA
UCLK
VOHU
VDD-0.5
－
－
V When current load =-5.0mA
【Output L voltage】
TGCLK
VOLT
－
－
0.5
V When current load =5.0mA
VCLK
VOLV
－
－
0.5
V When current load =5.0mA
UCLK
VOLU
－
－
0.5
V When current load =5.0mA
【Pull-Up resistance value】
TGCLK_SEL1
Specified by a current value
TGCLK_SEL2
Pull-up
125
250
375
KΩ ^{running when a voltage of 0V is}
R
applied to a measuring pin.
(R=VDD／I)
【Pull-Down resistance value】
TGCLK_EN, TGCLK_PD
Specified by a current value
VCLK_EN, VCLK_PD
Pull-down
25
50
75
KΩ ^{running when a VDD is applied to}
R
a measuring pin.
(R=VDD／I)
【Output frequency】
TGCLK SEL1:L SEL2:L TGCLK1
24.000000
MHz XTAL×(48/4)/6
TGCLK SEL1:L SEL2:H TGCLK2
30.000000
MHz XTAL×(60/4)/6
TGCLK SEL1:H
TGCLK3
36.000000
MHz XTAL×(54/3)/6
VCLK
VCLK
27.000000
MHz XTAL×(54/3)/8
UCLK
UCLK
12.000000
MHz XTAL output
【Output waveform】
Duty
Duty
45
50
55
％ Measured at a voltage of 1/2 of VDD
Rise time
Period of transition time required
Tr
2.0
nsec for the output to reach 80% from
20% of VDD.
Fall time
Period of transition time required
Tf
2.0
nsec for the output to reach 20% from
【Jitter】
80% of VDD.
Period-Jitter 1σ
P-J1σ
50
psec ※1
Period-Jitter MIN-MAX
【Output Lock-Time】
P-J
MIN-MAX
Tlock
※2
300
psec
1
msec ※3
Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to XTALIN.
If the input frequency is set to 12.000000MHz, the output frequency will be as listed above.
Common to BU2394KN, BU2396KN
※1 Period-Jitter 1σ
This parameter represents standard deviation (=1σ) on cycle distribution data at the time when the output clock cycles are
sampled 1000 times consecutively with the TDS7104 Digital Phosphor Oscilloscope of Tektronix Japan, Ltd.
※2 Period-Jitter MIN-MAX
This parameter represents a maximum distribution width on cycle distribution data at the time when the output clock cycles are
sampled 1000 times consecutively with the TDS7104 Digital Phosphor Oscilloscope of Tektronix Japan, Ltd.
※3 Output Lock-Time
The Lock-Time represents elapsed time after power supply turns ON to reach a 3.0V voltage, after the system is switched from
Power-Down state to normal operation state, or after the output frequency is switched, until it is stabilized at a specified frequency,
respectively.
3/16