BU2394KN_08 Datasheet, PDF (2/17 Pages) Rohm – 3ch Clock Generator for Digital Cameras

●Recommended Operating Range
Parameter
Symbol
Limit
Unit
Supply voltage
VDD
3.0～3.6
Ｖ
Input H voltage
VINH
0.8VDD～VDD
Ｖ
Input L voltage
VINL
0.0～0.2VDD
Ｖ
Operating temperature
Topr
-5～70
℃
Output load
CL
15(MAX)
pF
● Electrical characteristics
BU2394KN(VDD=3.3V, Ta=25℃, unless otherwise specified.)
XTAL_SEL=H with crystal oscillator at a frequency of 28.636363 MHz, while XTAL_SEL=L at 14.318182 MHz
Parameter
Symbol
Min.
【Action circuit current】
IDD
－
Limit
Typ.
45
Max.
60
Unit
Condition
mA At no load
【Output H voltage】
CLK1
VOH1
VDD-0.5
VDD-0.2
－
V When current load = - 9.0mA
CLK2
VOH2
VDD-0.5
VDD-0.2
－
V When current load = - 7.0mA
REF_CLK
VOHR
VDD-0.5
VDD-0.2
－
V When current load = - 4.5mA
【Output L voltage】
CLK1
VOL1
－
0.2
0.5
V When current load =11mA
CLK2
VOL2
－
0.2
0.5
V When current load =9.0mA
REF_CLK
VOLR
－
0.2
0.5
V When current load =5.5mA
【Pull-Up resistance value】
FS1, FS2, FS3,
Specified by a current value
CLK2ON, XTAL_SEL
Pull-Up
125
250
375
Ω ^{running when a voltage of 0V is}
R
applied to a measuring pin.
(R=VDD／I)
【Output frequency】
CLK1 FS2:H FS3:H
Fclk1-1
－
135.000000
－
MHz XTAL×(1188/63)/2
CLK1 FS2:H FS3:L
Fclk1-2
－
108.000000
－
MHz XTAL×(1056/70)/2
CLK1 FS2:L FS3:L
Fclk1-3
－
98.181818
－
MHz XTAL×(864/63)/2
CLK1 FS2:L FS3:H
Fclk1-4
－
110.000000
－
MHz XTAL×(968/63)/2
CLK2
Fclk2-2
－
48.008022
－
MHz XTAL×(228/17)/4
REF_CLK FS1:H
Fref1-1
－
14.318182
－
MHz XTAL Output
REF_CLK FS1:L
Fref1-2
－
17.734450
－
MHz XTAL×(706/57)/10
【Output waveform】
Duty1 100MHz or less
Duty1
45
50
55
％ ^{Measured at a voltage of 1/2 of}
VDD
Duty2 100MHz or more
Duty2
－
50
－
％ ^{Measured at a voltage of 1/2 of}
VDD
Rise time
Period of transition time required
Tr
－
2.5
－
nsec for the output to reach 80% from
20% of VDD.
Fall time
Period of transition time required
Tf
－
2.5
－
nsec for the output to reach 20% from
【Jitter】
80% of VDD.
Period-Jitter 1σ
P-J1σ
－
30
－
psec ※1
Period-Jitter MIN-MAX
P-J
－
180
－
※2
psec
MIN-MAX
【Output Lock-Time】
Tlock
－
－
1
msec ※3
Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to XTALIN. If the
input frequency is set to values shown below, the output frequency will be as listed above.
When XTAL_SEL is set to H, the input frequency on XTALIN will be 28.636363 MHz.
When XTAL_SEL is set to L, the input frequency on XTALIN will be 14.318182 MHz.
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