BU21072MUV_16 Datasheet, PDF (3/40 Pages) Rohm – Capacitive Switch Controller ICs

BU21072MUV / BU21078MUV / BU21078FV
Pin Descriptions
Number
Name Type
BU21072MUV BU21078MUV BU21078FV
Function
-
1
11
SIN12 Ain
Capacitive Touch Sensor12
2
2
12
SIN2 Ain
Capacitive Touch Sensor2
-
3
13
SIN11 Ain
Capacitive Touch Sensor11
3
4
14
SIN1 Ain
Capacitive Touch Sensor1
4
5
15
SIN0 Ain
Capacitive Touch Sensor0
5
6
16
AVDD Power LDO output for analog blocks
6
7
17
VDD Power Power
7
8
18
DVDD Power LDO output for digital blocks
8
9
19
VSS GND Ground
9
10
20
TEST In
Test input
10
11
21
SCL InOut Host I/F clock input
11
12
22
SDA InOut Bi-directional Host I/F Data
12
13
23
INT
Out
Interrupt output
13
14
24
LED0 Out
LED control with PWM output0
14
15
25
LED1 Out
LED control with PWM output1
15
16
26
LED2 Out
LED control with PWM output2
16
17
27
LED3 Out
LED control with PWM output3
17
18
28
LED4 Out
LED control with PWM output4
18
19
1
LED5 Out
LED control with PWM output5
-
20
2
LED6 Out
LED control with PWM output6
-
21
3
LED7 Out
LED control with PWM output7
19
-
-
SIN9 Ain
Capacitive Touch Sensor9
20
-
-
SIN8 Ain
Capacitive Touch Sensor8
21
22
4
SIN7 Ain
Capacitive Touch Sensor7
22
23
5
SIN6 Ain
Capacitive Touch Sensor6
-
24
6
SIN13 Ain
Capacitive Touch Sensor13
23
25
7
SIN5 Ain
Capacitive Touch Sensor5
-
26
8
SIN14 Ain
Capacitive Touch Sensor14
24
27
9
SIN4 Ain
Capacitive Touch Sensor4
1
28
10
SIN3 Ain
Capacitive Touch Sensor3
Note
Power
Please connect to Ground level
Active High Interrupt
Active High
Active High
Active High
Active High
Active High
Active High
Active High
Active High
AVDD
AVDD
AVDD
AVDD
AVDD
VDD
-
VDD
-
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
Initial
Condition
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
-
-
-
-
-
Hi-Z
Hi-Z
"L"
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
"L"
"L"
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
I/O
Equivalence
Circuits
Fig.5
Fig.5
Fig.5
Fig.5
Fig.5
-
-
-
-
Fig.6
Fig.6
Fig.6
Fig.7
Fig.7
Fig.7
Fig.7
Fig.7
Fig.7
Fig.7
Fig.7
Fig.7
Fig.5
Fig.5
Fig.5
Fig.5
Fig.5
Fig.5
Fig.5
Fig.5
Fig.5
Initial Condition is at that power-on-reset is active.
I/O Equivalence Circuits
ASW
AIN
I
AVDD
CIN
PAD
I
VDD
PAD
I
VDD
PAD
OEN
OEN
Figure 5. I/O equivalence circuit (a)
Figure 6. I/O equivalence circuit (b)
Figure 7. I/O equivalence circuit (c)
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14.Jul.2016 Rev.004