BU97501KV Datasheet, PDF (24/33 Pages) Rohm – Integrated RAM for display data

BU97501KV
Datasheet
Cautions in Power-On Sequence
Power-On Reset (POR) Circuit
This LSI has “P.O.R” (Power-On Reset) circuit and Software Reset function.
When the power is ON, IC internal circuit and reset pass through unstable low-voltage region.
Internal IC is not totally reset because VDD rises and this may result to malfunction.
Thus, POR circuit and function of software reset are installed in order to prevent this.
Please follow the following recommended Power-On sequences to allow the reset action to complete.
Set the power up conditions to meet the recommended tR, tF, tOFF, and Vbot spec below in order to ensure
P.O.R operation.
VDD
tF
tR
tOFF
Vbot
tR, tF, tOFF, Vbot recommended conditions
tR
Less than
5ms
tF
Less than
5ms
tOFF
More than
150ms
Vbot
Less than
0.1V
Figure 23. Power ON/OFF waveform
If it is difficult to meet above conditions, execute the following sequence after Power-On.
(1) Set CSB to High
(2) Clear CSB to Low and then issue a SWRST command.
VDD
CSB
Min 1ms
Min 50ns
SWRST
Command
Figure 24. SWRST Command Sequence
Power Up Sequence and Power Down Sequence
To prevent the malfunction, in power up sequence, VDD shall be turned on before VLCD.
In power down sequence, VDD shall be turned off after VLCD.
Please satisfies VLCD≥VDD、t1≧0ns
t1
t1
VLCD
VDD
Figure 25. Power On/Off Sequence
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11.Apr.2014 Rev.004