BU97501KV Datasheet, PDF (19/33 Pages) Rohm – Integrated RAM for display data

BU97501KV
Datasheet
Detailed command description
Sleep Control (SLP CTRL)
MSB
LSB
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
1 P3 P2 * *
(* : Don’t care)
P3, P2: Normal mode/Sleep mode switching control data
These control data bits select Key Scan Output Pins KS1 to KS6 States of during Key Scan Standby.
Control
bits
P3 P2
Mode
Internal
OSC
Segment
Output Pin States During Key Scan
outputs/Common
Standby
Outputs
KS1 KS2 KS3 KS4 KS5 KS6
Reset
Conditions
0 0 Normal enabled
Operating
HHHHHH
01
Sleep
L
L
L
L
L
H
○
10
Sleep
disabled
Low(VSS)
L
L
L
L
HH
11
Sleep
HHHHHH
（Note10）When DRV CTRL3（P3, P2）=（1, 1）, KS1 to KS6 outputs are selected as Segment outputs.
Segment Control (SEG CTRL)
MSB
LSB
D7 D6 D5 D4 D3 D2 D1 D0
1
0
1
1 P3 P2 P1 *
(* : Don’t care)
P3 to P1 : Segment Output / General purpose output switching control data
These control bits select the function of the S1/P1 to S4/P4 output pins.
(Segment Output Pins or General Purpose Output Pins).
Control bits
Status of the pins
Reset
conditions
P3 P2 P1 S1/P1 S2/P2 S3/P3 S4/P4
0
0
0 S1 S2 S3 S4
○
0
0
1 P1 S2 S3 S4
0
1
0 P1 P2 S3 S4
0
1
1 P1 P2 P3 S4
1
0
0 P1 P2 P3 P4
(Note11) Sn(n=1 to 4) : assigned as a Segment Output pin
Pn(n=1 to 4) : assigned as a General Purpose Output pin
Relationship of bit assignment between general purpose output pin and bit in DDRAM
Output Pin
Corresponding bit in DDRAM
1/3 Duty
1/4 Duty
S1/P1
D1
D1
S2/P2
D4
D5
S3/P3
D7
D9
S4/P4
D10
D13
In case of 1/4 Duty mode and S4/P4 is configured as a general purpose output pins.
S4/P4 is set to HIGH (VLCD level) if D13 is set to “1” in DDRAM.
S4/P4 is cleared to LOW (VSS level) if D13 is set to “0” in DDRAM.
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TSZ02201-0P4P0D300390-1-2
11.Apr.2014 Rev.004