BU8710AKS Datasheet, PDF (23/32 Pages) Rohm – 4-channel ADPCM transcoder for digital cordless telephone base stations

Communication ICs
BU8710AKS
2) Relation between clock frequency and data word length
Serial data is interfaced in two lengths, 8 bits and 4 bits.
For 8-bit data, the transmission speed is 64kbps, and for
4-bit data, the speed is 32kbps.
1. For 64 kbps transmission
2. For 32 kbps transmission
The clock frequency is set within a range of 64kHz to
The clock frequency is set within a range of 32kHz to
8MHz. This transmission speed is applicable in the fol-
8MHz. This transmission speed is applicable in the fol-
lowing cases.
lowing cases.
S For encoder input and decoder output when normal
S For decoder input and encoder output when normal
ADPCM calculation is being carried out.
ADPCM calculation is being carried out.
S For encoder and decoder input and output in the data
S For decoder input and encoder output in the data loop
through mode.
back mode.
S For encoder input and decoder output in the data loop
back mode.
3) Output delays in relation to input
After data is input, it takes a certain amount of time for the
data to undergo ADPCM calculation before being output.
This section explains delays in data output in relation to
data input.
First, we will look at the relationship between the timing
at which serial data is input from and output to an external
source, and internal operation.
In Figures 21 to 24, the timings for items 1 to 3 and 7
to 9 are indicated as seen from the pins, while items 4
to 6 show internal signal states. The items are explained
below, in numeric order.
1. An 8-bit or 4-bit data row is input serially based on the
input clock 1 , Input Enable signal 2 , and input data 3 .
Figures 21 to 24 show the states for the normal mode
only. The timing for the synchronous mode is equivalent
to that for the long frame in the normal mode.
2. Immediately after the 8-bit or 4-bit data has been in-
put serially at step 1 , the calculation start pulse 4 is
generated. Also, at this point, the data which is the target
of the calculation 5 , which has been converted from seri-
al to parallel data, is prepared as parallel 8-bit or 4-bit
data.
3. The calculation is carried out on the target data.
Calculation is completed before the next calculation start
pulse 4 is received, and the resulting data 6 is updated
by the calculation start pulse 4 . In the data through and
data loop back modes as well, the ADPCM calculation
processing is omitted, but the timing at which the result-
ing data 6 is updated remains the same.
4. The data resulting from the calculation 6 is latched
in order to be converted from parallel to serial data. With
a short frame in the normal mode, this is done following
one cycle after the rising edge of the Output Enable sig-
nal 8 , at the rising edge of the output clock 7 . With a
short frame in the normal mode, and in the synchronous
mode, this is done at the rising edge of the Output Enable
signal. In addition, the 8-bit or 4-bit data is output serially
based on the output clock, the Output Enable signal 8 ,
and the Output Data signal 9 .
[Supplementary information for Figures 21 X 24]
S SDi (k) ^{G G G G} Serial input data targeted for calculation
S PDi (k) ^{G G G G} Parallel input data targeted for calculation
S PDO (k) ^{G G G G} Parallel output data resulting from cal-
culation
S SDo (k) ^{G G G G} Serial output data resulting from calcula-
tion
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