BD9757MWV_10 Datasheet, PDF (19/24 Pages) Rohm – Switching Regulator IC

BD9757MWV
Technical Note
●Notes for use
1.) Absolute Maximum Ratings
Although the quality of this product has been tightly controlled, deterioration or even destruction may occur if the absolute
maximum ratings, such as for applied pressure and operational temperature range, are exceeded. Furthermore, we are
unable to assume short or open mode destruction conditions. If special modes which exceed the absolute maximum
ratings are expected, physical safely precautions such as fuses should be considered.
2.) GND Potential
The potential of the GND pin should be at the minimum potential during all operation status. In addition, please try to do
not become electric potential below GND for the terminal other than NON6 including the transient phenomenon in practice.
Please do not go down below 0.3V for the NON6 terminal with transient phenomenon and the like when you use.
3.) Heat Design
Heat design should consider tolerance dissipation (Pd) during actual use and margins which should be set with plenty of
room.
4.) Short-circuiting Between Terminals and Incorrect Mounting
When attaching to the printed substrate, pay special attention to the direction and proper placement of the IC. If the IC is
attached incorrectly, it may be destroyed. Destruction can also occur when there is a short, which can be caused by
foreign objects entering between ouputs or an output and the power GND.
5.) Operation in Strong Magnetic Fields
Exercise caution when operating in strong magnet fields, as errors can occur.
6.) About common impedance
Please do sufficient consideration for the wiring of power source and GND with the measures such as lowering common
impedance, making ripple as small as possible (making the wiring as thick and short as possible, dropping ripple from
L.C) and the like.
7.) STB terminal voltage
Please set STB terminal voltage below 0.3V when each channel is put in stand-by state, and set it above 1.5V when each
channel is put in working condition. Please use the condenser below 0.01μF when the condenser is connected to the
STB terminal. As it will become the cause of the malfunction.
8.) Heat Protection Circuit (TSD circuit)
This IC has a built-in Temperature Protection Circuit (TSD circuit). The temperature protection circuit (TSD circuit) is only
to cut off the IC from thermal runaway, and has not been designed to protect or guarantee the IC. Therefore, the user
should not plan to activate this circuit with continued operation in mind.
9.) Because there are times when rush current flows instantaneously in internal logical uncertain state at the time of power
source turning on with CMOS IC, please pay attention to the power source coupling capacity, the width of GND pattern
wiring and power source, and the reel.
10.) Because there are times when rush current flows instantaneously due to the order of power source throwing in, lag with
CMOS IC where it has plural power sources, please pay attention to the power source coupling capacity, the width of
GND pattern wiring and power source, and the reel.
11.) IC Terminal Input
This IC is a monolithic IC, and between each element there is a P+ isolation and P substrate for element separation.
There is a P-N junction formed between this P-layer and each element’s N-layer, which makes up various parasitic
elements. For example, when resistance and transistor are connected with a terminal as in Fig.33:
○When GND>(terminal A) at the resistance, or GND>(terminal B) at the transistor (NPN),
the P-N junction operates as a parasitic diode.
○Also, when GND>(terminal B) at the transistor, a parasitic NPN transistor operates by the N-layer of other elements
close to the aforementioned parasitic diode.
With the IC’s configuration, the production of parasitic elements by the relationships of the electrical potentials is
inevitable. The operation of the parasitic elements can also interfere with the circuit operation, leading to malfunction
and even destruction. Therefore, uses which cause the parasitic elements to operate, such as applying voltage to the
input terminal which is lower than the GND (P-substrate), should be avoided.
(Terminal A)
P⁺
N
P Board
Resistance
Transistor (NPN)
(Terminal B) _C
B
E
P
N
P⁺
N
P⁺
N
N_P
P⁺
N
Parasitic Element
P Board
GND
Parasitic Element
GND
GND
(Terminal A)
N
GND
Parasitic Element
Fig.33 Simple Structure of Bipolar IC (Sample)
www.rohm.com
© 2010 ROHM Co., Ltd. All rights reserved.
19/20
2010.11 - Rev.A