BD9132MUV_14 Datasheet, PDF (19/26 Pages) Rohm – Synchronous Buck Converter with Integrated FET

BD9132MUV
Operational Notes – continued
11. Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
12. Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should
be avoided.
Resistor
Transistor (NPN)
Pin A
Pin A
Pin B
C
B
E
Pin B
P⁺
N
N
Parasitic
Elements
P
P⁺
N
N
P Substrate
GND
Parasitic
Elements
N ^P+
N _{P N P}⁺ _N
P Substrate
Parasitic
GND GND
Elements
Figure 38. Example of monolithic IC structure
B
N Region
close-by
C
E
Parasitic
Elements
GND
13. Thermal Shutdown Circuit(TSD)
This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always
be within the IC’s power dissipation rating. If however the rating is exceeded for a continued period, the junction
temperature (Tj) will rise which will activate the TSD circuit that will turn OFF all output pins. When the Tj falls below
the TSD threshold, the circuits are automatically restored to normal operation.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from
heat damage.
14. Selection of Inductor
It is recommended to use an inductor with a series resistance element (DCR) 0.1Ω or less. Especially, note that use
of a high DCR inductor will cause an inductor loss, resulting in decreased output voltage. Should this condition
continue for a specified period (soft start time + timer latch time), output short circuit protection will be activated and
output will be latched OFF. When using an inductor over 0.1Ω, be careful to ensure adequate margins for variation
between external devices and this IC, including transient as well as static characteristics. Furthermore, in any case, it
is recommended to start up the output with EN after supply voltage is within.
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TSZ22111・15・001
19/22
TSZ02201-0J3J0AJ00140-1-2
03.Oct.2014 Rev.002