BD9132MUV_14 Datasheet, PDF (14/26 Pages) Rohm – Synchronous Buck Converter with Integrated FET

BD9132MUV
(4) Calculating RITH , CITH for Phase Compensation
Since the Current Mode Control is designed to limit an inductor current, a pole (phase lag) appears in the low
frequency area due to a CR filter consisting of an output capacitor and a load resistance, while a zero (phase lead)
appears in the high frequency area due to the output capacitor and its ESR. Therefore, the phases are easily
compensated by adding a zero to the power amplifier output with C and R as described below to cancel a pole at the
power amplifier.
A
Gain
[dB] ⁰
0
Phase
[deg]
-90
fp(Min)
fp 
1
2  R_O  C_O
fp(Max)
IOUTMin
IOUTMax
fZ(ESR)
f_Z
(ESR)

2

1
ESR C_O
Pole at power amplifier
When the output current decreases, the load resistance
RO increases and the pole frequency decreases.
fpMin 
1
Figure 31. Open Loop Gain Characteristics
2  R_OMax  C_O
Hz  with lighterload
fpMax 
1
2  R_OMin  C_O
Hz  with heaiver load
A
Gain
[dB]
0
0
Phase
[deg]
-90
fZ(Amp)
Zero at Power Amplifier
Increasing capacitance of the output capacitor lowers the
pole frequency while the zero frequency does not change.
(This is because when the capacitance is doubled, the
capacitor ESR is reduced to half.)
f_Z ( Amp)

2
1
 R_ITH
 C_ITH
Figure 32. Error Amp Phase Compensation Characteristics
Rf
C1
VCC
CIN
EN
PVCC
VCC
ADJ
CBST
L
ITH
GND, PGND
SW
RITH
CO
VOUT
CITH
R2
R1
Figure 33. Typical Application
Stable feedback loop may be achieved by canceling the pole fp (Min) produced by the output capacitor and the load
resistance with CR zero correction by the error amplifier.
fz(Amp)= fp(Min)

1

1
2  R_ITH  C_ITH 2  R_OMax  C_O
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TSZ22111・15・001
14/22
TSZ02201-0J3J0AJ00140-1-2
03.Oct.2014 Rev.002