BU90R102 Datasheet, PDF (18/29 Pages) Rohm – Support clock frequency from 8MHz up to 160MHz

BU90R102
Datasheet
LVDS Input Data Mapping (Continued)
Table 10. LVDS Input Data Mapping (Single-in/Dual-out mode, MODE<1:0>=HL)
1st Pixel Data
2nd Pixel Data
LVDS
Input Data
(1st Pixel Data)
Mapping Mode1
(Output Pin Name)
Mapping Mode2
(Input Pin Name)
LVDS
Input Data
(1st Pixel Data)
Mapping Mode1
(Output Pin Name)
Mapping Mode2
(Input Pin Name)
RA10(n)
RA11(n)
RA12(n)
RA13(n)
RA14(n)
RA15(n)
RA16(n)
RB10(n)
RB11(n)
RB12(n)
RB13(n)
RB14(n)
RB15(n)
RB16(n)
RC10(n)
RC11(n)
RC12(n)
RC13(n)
RC14(n)
RC15(n)
RC16(n)
RD10(n)
RD11(n)
RD12(n)
RD13(n)
RD14(n)
RD15(n)
RD16(n)
RE10(n)
RE11(n)
RE12(n)
RE13(n)
RE14(n)
RE15(n)
RE16(n)
R14
R15
R16
R17
R18
R19
G14
G15
G16
G17
G18
G19
B14
B15
B16
B17
B18
B19
HSYNC
VSYNC
DE
R12
R13
G12
G13
B12
B13
CONT11
R10
R11
G10
G11
B10
B11
CONT12
R12
R13
R14
R15
R16
R17
G12
G13
G14
G15
G16
G17
B12
B13
B14
B15
B16
B17
HSYNC
VSYNC
DE
R18
R19
G18
G19
B18
B19
CONT11
R10
R11
G10
G11
B10
B11
CONT12
RA10(n+1)
RA11(n+1)
RA12(n+1)
RA13(n+1)
RA14(n+1)
RA15(n+1)
RA16(n+1)
RB10(n+1)
RB11(n+1)
RB12(n+1)
RB13(n+1)
RB14(n+1)
RB15(n+1)
RB16(n+1)
RC10(n+1)
RC11(n+1)
RC12(n+1)
RC13(n+1)
RC14(n+1)
RC15(n+1)
RC16(n+1)
RD10(n+1)
RD11(n+1)
RD12(n+1)
RD13(n+1)
RD14(n+1)
RD15(n+1)
RD16(n+1)
RE10(n+1)
RE11(n+1)
RE12(n+1)
RE13(n+1)
RE14(n+1)
RE15(n+1)
RE16(n+1)
R24
R25
R26
R27
R28
R29
G24
G25
G26
G27
G28
G29
B24
B25
B26
B27
B28
B29
HSYNC
VSYNC
DE
R22
R23
G22
G23
B22
B23
CONT21
R20
R21
G20
G21
B20
B21
CONT22
R22
R23
R24
R25
R26
R27
G22
G23
G24
G25
G26
G27
B22
B23
B24
B25
B26
B27
HSYNC
VSYNC
DE
R28
R29
G28
G29
B28
B29
CONT21
R20
R21
G20
G21
B20
B21
CONT22
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02.Oct.2014 Rev.001