BD9123MUV_14 Datasheet, PDF (17/28 Pages) Rohm – Synchronous Buck Converter with Integrated FET

BD9123MUV
Datasheet
(4) Determination of RITH, CITH that works as a phase compensator
As the Current Mode Control is designed to limit the inductor current, a pole (phase lag) appears in the low frequency
area due to a CR filter consists of an output capacitor and a load resistance, while a zero (phase lead) appears in the
high frequency area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a zero
to the power amplifier output with C and R as described below to cancel a pole at the power amplifier.
A
Gain
[dB] ⁰
0
Phase
[deg]
fp(Min)
fp(Max)
IOUTMin
IOUTMax
fZ(ESR)
fp 
1
2  R_O C_O
f _{Z ESR}

2
1
 ESRC_O
Pole at power amplifier
When the output current decreases, the load resistance Ro
increases and the pole frequency lowers.
-90
fp_{Min}

2
1
 R_OMax  C_O
Hz withlighterload
Figure 37. Open Loop Gain Characteristics
fp_{Max}

2

1
R_OMin
C_O
Hz with heavierload
A
Gain
[dB]
fZ(Amp)
Zero at Power Amplifier
Increasing capacitance of the output capacitor lowers the
pole frequency while the zero frequency does not change.
(This is because when the capacitance is doubled, the
capacitor ESR is reduced to half.)
0
0
Phase
[deg]
-90
f_{Z Amp}

2

1
R_ITH
 C_ITH
Figure 38. Error Amp Phase Compensation Characteristics
VCC
VCC
CIN
RPG
EN
VCC,PVCC
VOUT
VOUT
PGOOD
VID<2:0>
VID<2:0)
L
ITH
SW
GND,PGND
RITH
CO
CITH
VOUT
Figure 39. Typical Application
Stable feedback loop may be achieved by canceling the pole fp (Min) produced by the output capacitor and the load
resistance with CR zero correction by the error amplifier.
f _{Z Amp}  fp_{Min}

1

1
2  R_ITH  C_ITH 2  R_{O Max}  C_O
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02.Oct.2014 Rev.002