BU9829GUL-W_12 Datasheet, PDF (16/27 Pages) Rohm – WLCSP EEPROM

BU9829GUL-W (16Kbit)
Datasheet
●EEPROM soft ware
○READ, VSET_READ, RDSR Command cancel
Cancel of these commands is possible by changing CSB pin to “HIGH” in all sections.
OPECODE
ADDRESS
DATA
OPECODE
DATA
8bit
8bit
8bit
Cancel is possible
Figure 39. READ, VSET_READ Cancel Timing
8bit
8bit
Cancel is possible
Figure 40. RDSR Cancel Timing
○WRITE, PAGE_WRITE, VSET_WRITE, WRSR Command cancel
Cancel of these write command is possible by changing CSB pin to “HIGH” in opecode, address and data input sections
(section a to b), but it is impossible after data input section (section c to d), if Vcc1 is OFF during tE/W, please write again
because write data is not guaranteed in specified address, if SCK and CSB rise at the same time in section C, command
is instability. It is recommend to rise CSB in “SCK=L” section.
OPECODE ADDRESS
DATA(n)
tE/W
SCK
8bit
8bit
a
8bit
b
d
c
SI
AN ENLARGEMENT
D7 D6 D5 D4 D3 D2 D1 D0
b
c
Figure 41. WRITE, PAGE_WRITE, VSET_WRITE READ VSET_READ Cancel Timing
OPECODE
8bit
a
DATA(n)
8bit
b
c
tE/W
8bit
d
SCK ^{14 15 16 17}
AN ENLARGEMENT
SI
D1 D0
b
c
d
Figure 42. WRSR Cancel Timing
○WREN, WRDI command cancel
Cancel of these commands is possible by changing CSB pin to “HIGH” of opecode to rising 8 clk, but it is impossible after
rising 8 clk. In the case, please send WREN or WRDI cancel timing command again.
OPECODE
8bit
a
7
8
9
AN ENLARGEMENT
b
a
b
Figure 43. WREN, WRDI Cancel Timing
●Data polling
If RDSR command is carried out daring tE/W, according to out put data ( R / B bit), to monitor READY/BUSY state is
possible. Because of this, it is possible to send next command earlier than regular programming time (tE/W MAX=5ms).
If R / B bit is “1”, EEPROM’s state is “BUSY”. If this becomes “0”, it is possible to send next command to change
EEPROM to “READY” state. Status register data read by this command in tE/W is not data written by WRSR command but
old data before. Status register data in each section is shown below.
CSB
SCK
SI
SO
READ STATUS
REGISTOR
a=0Ch
During WRSR Command(tE/W）
BUSY
READY
WRITE STATUS
REGISTOR
b=(00h)
READ STATUS
REGISTOR
c=0Fh
READ STATUS
REGISTOR
d=0Ch
READ STATUS
REGISTOR
e=00h
Figure 44. Status register data in each section
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TSZ22111・15・001
16/23
TSZ02201-0R2R0G100400-1-2
28.AUG.2012 Rev.001