BU9829GUL-W_12 Datasheet, PDF (14/27 Pages) Rohm – WLCSP EEPROM

BU9829GUL-W (16Kbit)
Datasheet
3.READ
The data stored in the memory are clocked out after “Read” instruction is received. After CSB goes low, the address need
to be sent following by Op.code of “Read”. The data at the address specified are clocked out from D7 to D0, which is start
at the falling edge of 23th clock. This device has the auto-increment feature that provides the whole data of the memory
array with one read command, outputs the next address data following the addressed 8bits of data by keeping SCK
clocking. When the highest address is reached, the address counter rolls over to the lowest address allowing the
continuous read cycle.
CSB
～～
～～
～～
SCK
～～
0
1
2
3
4
5
6
7
8
～～
14
23 24
～～
～～
～～
SI
00 0
0
0
0
1
1 * * _{～ ～} 0 A10 _{～ ～} A1 A0
～～
SO ^Hi-Z
～～
～～
Figure 33. READ CYCLE TIMING
～～
D7 D6 _{～ ～}
30
D2 D1 D0
*=Don't care
4. WRITE
This “Write” command writes 8bits of data into the specified address. After CSB goes low, the address need to be sent
following by Op.code of “Write”. Between the rising edge of the 29th clock and it of the 30th clock, the rising edge of CSB
initiates high voltage cycle, which writes the data into non-volatile memory array, but the command is cancelled if CSB is
high except that period. It takes maximum 5ms in high voltage cycle (tE/W). The device does not receive any command
except for “Read Status Register” command during this high voltage cycle. This device is capable of writing the data of
maximum 32byte into memory array at the same time, which keep inputting two or more byte data with CSB “L” after
8bits of data input. For this Page Write commands, the eight higher order bits of address are set, the six low order
address bits are internally incremented by 5bits of data input. If more than 16 words, are transmitted the address counter
“roll over”, and the previous transmitted data is overwritten.
CSB
SCK
SI
～～
～～
～～
0 1 2 3 4 56 7 8
14 _{～ ～}
00 0 0 0 0
10
*
～～
～～
～ ～ ^{0 A10} ～ ～
23 24
A1 A0 D7 D6
SO ^Hi-Z
～～
～～
Figure 34. WRITE CYCLE TIMING
～～
～～
30 31
～～
～ ～ ^{D2 D1 D0}
～～
*=Don't care
5. RDSR (READ STATUS REGISTER)
The data stored in the status register is clocked out after “Read Status Register” instruction is received.
After CSB goes low, Op.colde of “Read Status Register” need to sent. The data stored in the status register is clocked out
of the device on the falling edge of 7th clock. Bit7, Bit6, Bit5 and Bit4 in the status register are read as 0.
This device has the auto-increment feature as well as “Read” that output the 8bits of the same data following it to keep
SCK clocking. It is possible to see ready and busy state by executing this command during tE/W. If more than 16 words,
are transmitted the address counter “roll over” and the previous transmitted data is overwritten.
CSB
SCK
0 1 2 3 4 5 ^{6 7} 8 ⁹ 10 ¹¹ 12 13 ^{14 15}
SI
00 0 0 0
SO
Hi-Z
1 01
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0 0 0 0 BP1 BP0 WEN R/B
Figure 35. READ STATUS REGISTER CYCLE TIMING
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
14/23
TSZ02201-0R2R0G100400-1-2
28.AUG.2012 Rev.001