BD9152MUV Datasheet, PDF (16/18 Pages) Rohm – Output 1.5A or Less High Efficiency Step-down Switching Regulator with Built-in Power MOSFET

BD9152MUV
Technical Note
●Cautions on use
1. Absolute Maximum Ratings
While utmost care is taken to quality control of this product, any application that may exceed some of the absolute maximum ratings
including the voltage applied and the operating temperature range may result in breakage. If broken, short-mode or open-mode may not
be identified. So if it is expected to encounter with special mode that may exceed the absolute maximum ratings, it is requested to take
necessary safety measures physically including insertion of fuses.
2. Electrical potential at GND
GND must be designed to have the lowest electrical potential In any operating conditions.
3. Short-circuiting between terminals, and mismounting
When mounting to pc board, care must be taken to avoid mistake in its orientation and alignment. Failure to do so may result in IC
breakdown. Short-circuiting due to foreign matters entered between output terminals, or between output and power supply or GND may
also cause breakdown.
4. Thermal shutdown protection circuit
Thermal shutdown protection circuit is the circuit designed to isolate the IC from thermal runaway, and not intended to protect and
guarantee the IC. So, the IC the thermal shutdown protection circuit of which is once activated should not be used thereafter for any
operation originally intended.
5. Inspection with the IC set to a pc board
If a capacitor must be connected to the pin of lower impedance during inspection with the IC set to a pc board, the capacitor must be
discharged after each process to avoid stress to the IC. For electrostatic protection, provide proper grounding to assembling processes
with special care taken in handling and storage. When connecting to jigs in the inspection process, be sure to turn OFF the power supply
before it is connected and removed.
6. Input to IC terminals
This is a monolithic IC with P⁺ isolation between P-substrate and each element as illustrated below. This P-layer and the N-layer of each
element form a P-N junction, and various parasitic element are formed.
If a resistor is joined to a transistor terminal as shown in Fig 42.
○P-N junction works as a parasitic diode if the following relationship is satisfied; GND>Terminal A (at resistor side), or GND>Terminal B
(at transistor side); and
○if GND>Terminal B (at NPN transistor side),
a parasitic NPN transistor is activated by N-layer of other element adjacent to the above-mentioned parasitic diode.
The structure of the IC inevitably forms parasitic elements, the activation of which may cause interference among circuits, and/or
malfunctions contributing to breakdown. It is therefore requested to take care not to use the device in such manner that the voltage lower
than GND (at P-substrate) may be applied to the input terminal, which may result in activation of parasitic elements.
Pin A
N
N ^P+
Parasitic element
Resistor
Pin A
P
P⁺ _N
P substrate
GND
Transistor (NPN)
C
B
Pin B
E
Parasitic
element
N _P+
Parasitic element
N
P
P⁺ _N
P substrate
GND
GND
B
C
E
Parasitic
element
GND
Other adjacent elements
Fig.42 Simplified structure of monorisic IC
7. Ground wiring pattern
If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal
GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due
to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of
external parts as well.
8 . Selection of inductor
It is recommended to use an inductor with a series resistance element (DCR) 0.15Ω or less. Note that use of a high DCR inductor will
cause an inductor loss, resulting in decreased output voltage. Should this condition continue for a specified period (soft start time + timer
latch time), output short circuit protection will be activated and output will be latched OFF. When using an inductor over 0.15Ω, be careful to
ensure adequate margins for variation between external devices and this IC, including transient as well as static characteristics.
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2009.05 - Rev.A