BU90T82 Datasheet, PDF (15/28 Pages) Rohm – Support clock frequency from 10MHz up to 174MHz

BU90T82
LVDS Output Data mapping Table (6B8B = L)
Datasheet
TCLKx+/-
x = 1, 2
Previous Cycle
Current Cycle
TAx+/-
R13
R12
G12
R17
R16
R15
R14
R13
R12
TBx+/-
G14
G13
B13
B12
G17
G16
G15
G14
G13
TCx+/-
B15
B14
DE
VSYNC
HSYNC
B17
B16
B15
B14
TDx+/-
R11
R10
L
B11
B10
G11
G10
R11
R10
Figure 15-(1). 8bit mode LVDS output mapping (MAP=H: JEIDA)
TCLKx+/-
x = 1, 2
Previous Cycle
Current Cycle
TAx+/-
R11
R10
G10
R15
R14
R13
R12
R11
R10
TBx+/-
G12
G11
B11
B10
G15
G14
G13
G12
G11
TCx+/-
B13
B12
DE
VSYNC
HSYNC
B15
B14
B13
B12
TDx+/-
R17
R16
L
B17
B16
G17
G16
R17
R16
Figure 15-(2). 8bit mode LVDS output mapping (MAP=L; VESA)
LVDS Output Data mapping Table (6B8B = H)
TCLKx+/-
x = 1, 2
Previous Cycle
Current Cycle
TAx+/-
R13
R12
G12
R17
R16
R15
R14
R13
R12
TBx+/-
G14
G13
B13
B12
G17
G16
G15
G14
G13
TCx+/-
B15
B14
DE
VSYNC
HSYNC
B17
B16
B15
B14
TDx+/-
HiZ
Figure 16-(1). 6bit mode LVDS output mapping (MAP=H; JEIDA)
TCLKx+/-
x = 1, 2
Previous Cycle
Current Cycle
TAx+/-
R11
R10
G10
R15
R14
R13
R12
R11
R10
TBx+/-
G12
G11
B11
B10
G15
G14
G13
G12
G11
TCx+/-
B13
B12
DE
VSYNC
HSYNC
B15
B14
B13
B12
TDx+/-
HiZ
Figure 16-(2). 6bit mode LVDS output mapping (MAP=L; VESA)
〇Product structure : Silicon monolithic integrated circuit
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TSZ22111 • 14 • 001
〇This product has no designed protection against radioactive rays
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TSZ02201-0L2L0H500270-1-2
23.Mar.2015 Rev.002