BD9134MUV_14 Datasheet, PDF (14/25 Pages) Rohm – Synchronous Buck Converter with Integrated FET

BD9134MUV
(4) Calculating RITH, CITH for Phase Compensation
Since the Current Mode Control is designed to limit the inductor current, a pole (phase lag) appears in the low
frequency area due to a CR filter consisting of an output capacitor and a load resistance, while a zero (phase lead)
appears in the high frequency area due to the output capacitor and it’s ESR. Therefore, the phases are easily
compensated by adding a zero to the power amplifier output with C and R as described below to cancel a pole at the
power amplifier.
fp(Min)
fp 
1
2  R_O  C_O
A
Gain
[dB] ⁰
fp(Max)
IOUTMin
IOUTMax
fZ(ESR)
fz_{ESR}

2
1
 ESR C_O
Pole at Power Amplifier
0
Phase
[deg]
-90
Figure 31. Open Loop Gain Characteristics
When the output current decreases, the load resistance
RO increases and the pole frequency decreases.
fp_{Min}

2
1
 R_OMax
 C_O
Hz withlighterload
fp_{Max}

2
1
 R_OMin
 C_O
Hz with heavierload
A
Gain
[dB]
fZ(Amp)
Zero at Power Amplifier
Increasing capacitance of the output capacitor lowers the pole
0
frequency while the zero frequency does not change. (This is
0
Phase
[deg]
-90
because when the capacitance is doubled, the capacitor ESR is
reduced to half.)
f z_{ Amp }

2
1
 R_ITH
 C_ITH
Figure 32. Error Amp Phase Compensation Characteristics
Rf
Cf
VCC
CIN
EN
PVCC
VCC
CBST
VOUT
ADJ
L
ITH
GND,PGND
SW
VOUT
RITH
ESR
RO
CITH
CO
Figure 33. Typical Application
Stable feedback loop may be achieved by canceling the pole fp (Min) produced by the output capacitor and the load
resistance with CR zero correction by the error amplifier.
fzAmp  fpMin

1

1
2  R_ITH  C_ITH 2  R_OMax  C_O
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
14/21
TSZ02201-0J3J0AJ00150-1-2
03.Oct.2014 Rev.002