BD9111NV_14 Datasheet, PDF (14/25 Pages) Rohm – Synchronous Buck Converter with Integrated FET

BD9111NV
Datasheet
(4) Calculating RITH, CITH for Phase Compensation
As the Current Mode Control is designed to limit the inductor current, a pole (phase lag) appears in the low frequency
area due to an CR filter consisting of an output capacitor and a load resistance, while a zero (phase lead) appears in
the high frequency area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a
zero to the power amplifier output with C and R as described below to cancel a pole at the power amplifier.
A
Gain
[dB] ⁰
0
Phase
[deg]
-90
fp(Min)
fp(Max)
IOUTMin
IOUTMax
fZ(ESR)
Figure 31. Open Loop Gain Characteristics
A
Gain
[dB]
0
0
Phase
[deg]
-90
fZ(Amp)
fp 
1
2  R_O  C_O
f _{Z ESR}

2

1
ESR C_O
Pole at power amplifier
When the output current decreases, the load resistance
Ro increases and the pole frequency decreases.
fp_{Min}

2
1
 R_OMax  C_O
fp_{Max}

2

1
R_OMin
 C_O
Hz  with lighterload
Hz  with heavier load
Zero at Power Amplifier
Increasing capacitance of the output capacitor lowers the
pole frequency while the zero frequency does not change.
(This is because when the capacitance is doubled, the
capacitor ESR is reduced to half.)
f _{Z Amp}

2
1
 R_ITH
 C_ITH
Figure 32. Error Amp Phase Compensation Characteristics
VCC
CIN
L
EN ^VCC,PVCC SW
VOUT
VOUT
CO
ITH
GND,PGND
RITH
CITH
VOUT
Figure 33. Typical Application
Stable feedback loop may be achieved by canceling the pole fp (Min) produced by the output capacitor and the load
resistance with CR zero correction by the error amplifier.
fz_{Amp}  fp_{Min}

1

1
2  R_ITH  C_ITH 2  R_OMax  C_O
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02.Oct.2014 Rev.002