BD9018KV Datasheet, PDF (14/17 Pages) Rohm – Step-down,High-efficiency Switching Regulators (Controller type)

BD9018KV
Technical Note
12）GND wiring pattern
When both a small-signal GND and high current GND are present, single-point grounding (at the set standard point) is
recommended, in order to separate the small-signal and high current patterns, and to be sure voltage changes stemming
from the wiring resistance and high current do not cause any voltage change in the small-signal GND. In the same way,
care must be taken to avoid wiring pattern fluctuations in any connected external component GND.
13）The SW pin
When the SW pin is connected in an application, its coil counter-electromotive force may give rise to a single electric
potential. When setting up the application, make sure that the SW pin never exceeds the absolute maximum value.
Connecting a resistor of several Ω will reduce the electric potential. (See Fig. 35)
Vcc
BOOT
OUTH
SW ^R
OUTL
DGND
Vo _{Fig. 35}
14) The output FET
The shoot-through may happen when the input parasitic capacitance of FET is extremely big. Less than or equal to
1200pF input parasitic capacitance is recommended. Please confirm operation on the actual application since this
character is affected by PCB layout and components.
15）This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.
P-N junctions are formed at the intersection of these Players with the N layers of other elements, creating a parasitic
diode or transistor. Relations between each potential may form as shown in the example below, where a resistor and
transistor are connected to a pin:
○ With the resistor, when GND＞ Pin A, and with the transistor (NPN), when GND＞Pin B:
The P-N junction operates as a parasitic diode
○ With the transistor (NPN), when GND＞ Pin B:
The P-N junction operates as a parasitic transistor by interacting with the N layers of elements in proximity to the
parasitic diode described above.
Parasitic diodes inevitably occur in the structure of the IC. Their operation can result in mutual interference between
circuits, and can cause malfunctions, and, in turn, physical damage or destruction. Therefore, do not employ any of the
methods under which parasitic diodes can operate, such as applying a voltage to an input pin lower than the (P
substrate) GND.
(PINA)
Resistor
Transistor（NPN）
(PINB)
C
BE
P⁺
N
P
P
P⁺
N
Parasitic element
GND
P⁺
N
P
N
P⁺
N
P substrate
GND
(PINB)
BC
E
GND
(PINA)
Parasitic element
Parasitic element or transistor
Parasitic element
or transistor
Fig. 36
Fig. 37
Fig. 38
Fig. 39
16) For applications where Vin and EN are directly connected, the output may overshoot. To avoid this issue it is
recommended to select the lower side of the feedback resistor to more than 47kΩ.
This restriction does not apply if the EN is individually turned on when the VCC is greater than 4.5V.
www.rohm.com
○^c 2010 ROHM Co., Ltd. All rights reserved.
14/16
2010.02 - Rev.A