BD52XX-2C Datasheet, PDF (13/24 Pages) Rohm – Free Time Delay Setting CMOS Voltage Detector (Reset) IC

BD52xx-2C Series BD53xx-2C Series
3. Timing Waveform
The following shows the relationship between the input voltage VDD and the output voltage VOUT when the power supply
voltage VDD is sweep up and sweep down.
VDD
VDD
Vref
Delay
Circuit
RL
VOUT
GND
VDD
VDET+ΔVDET
VDET
VOPL: <0.8V
①②③
VOUT
CT
CCT
Figure 31. BD52xx-2C Set-up
⑤
Hysteresis Voltage (ΔVDET)
t
④
⑤ ^{②③ ④ ⑤ ② â‘} 
undefined _tPLH
tPHL
tPLH
t
tPHL
undefined
Figure 32. Timing Diagram
① When the power supply turns on, the Output Voltage (VOUT) is undefined until VDD overcomes the Operating
Voltage Limit (VOPL).
② VOUT will turn to “Low” as VDD increases above VOPL but less than the Release Voltage (VDET+ΔVDET),
③ When VDD exceeds the Release Voltage (VDET+ΔVDET), delay time (tPLH) set by capacitor at CT pin (CCT)
will happen then VOUT will switch from “Low” to “High”.
④ VOUT will remain “High” until VDD do not fall below the Detection Voltage (VDET).
⑤ When VDD drops below VDET, VOUT will switch from “High” to “Low” with a delay of tPHL.
*The potential difference between the detection voltage and the release voltage is known as the Hysteresis
Voltage width (∆VDET). The system is designed such that the output will not toggle with power supply fluctuations
within this hysteresis width, preventing malfunctions due to noise.
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