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BD52XX-2C Datasheet, PDF (12/24 Pages) Rohm – Free Time Delay Setting CMOS Voltage Detector (Reset) IC
BD52xx-2C Series BD53xx-2C Series
Application Information
1. Explanation of Operation
For both the open drain type (Figure 29) and the CMOS output type (Figure 30), the detection and release voltages
are used as threshold voltages. When the voltage applied to the VDD pin reaches the applicable threshold voltage,
the VOUT pin voltage switches from either “High” to “Low” or from “Low” to “High”. BD52xx-2C series and
BD53xx-2C series have delay time function which set tPLH (output “Low” to ”High”) using an external capacitor
connected in CT pin (CCT). Because the BD52xx-2C series uses an open drain output type, it is necessary to connect
a pull up resistor to VDD or another power supply if needed [The output “High” voltage (VOUT) in this case becomes
VDD or the voltage of the other power supply].
VDD
Vref
Delay
Circuit
VDD
VOUT
Vref
Delay
Circuit
VOUT
GND
CT
Figure 29. (BD52xx-2C type internal block diagram)
GND
CT
Figure 30. (BD53xx-2C type internal block diagram)
2. Setting of Detector Delay Time
Delay time L~H (tPLH) is the time when VOUT rises to 1/2 of VDD after VDD rises up and beyond the release
voltage (VDET+∆VDET). The delay time (tPLH) at the rise of VDD is determined by delay coefficient, CT capacitor and
delay time when CT pin is open (tCTO) and calculated from the following formula. When CT capacitor ≥ 1nF, tCTO has
less effect and tPLH computation is shown on Example No.2. The result has ±50% tolerance within the operating
temperature range of -40°C to +125°C
Formula: (Ta=25°C)
𝑡𝑃𝐿𝐻 = 𝐶𝐶𝑇 × 𝐷𝑒𝑙𝑎𝑦 𝐶𝑜𝑒𝑓𝑓𝑖𝑐𝑖𝑒𝑛𝑡 + 𝑡𝐶𝑇𝑂 [s]
where:
CCT is the CT pin external capacitor
Delay Coefficient is equal to 5.55 x 106
tCTO is the delay time when CT=open Note1
Temperature
Ta = -40°C to +125°C
Delay Time (tCTO)
Min
Typ
Max
15µs
50µs
150µs
Note1: tCTO is design guarantee only; outgoing inspection is not done on all products.
Example No.1:
CT capacitor = 100pF
𝑡𝑃𝐿𝐻_𝑚𝑖𝑛 = (100 × 10−12 × 5.55 × 106) × 0.5 + 15 × 10−6 = 292µ𝑠
𝑡𝑃𝐿𝐻_𝑡𝑦𝑝 = (100 × 10−12 × 5.55 × 106) × 1.0 + 50 × 10−6 = 605µ𝑠
𝑡𝑃𝐿𝐻_𝑚𝑎𝑥 = (100 × 10−12 × 5.55 × 106) × 1.5 + 150 × 10−6 = 983µ𝑠
Example No.2:
CT capacitor = 1nF
𝑡𝑃𝐿𝐻_𝑡𝑦𝑝 = 1 × 10−9 × 5.55 × 106 = 5.55𝑚𝑠
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TSZ02201-0R7R0G300200-1-2
25.Apr.2016 Rev.001