BU9891GUL-W Datasheet, PDF (11/18 Pages) Rohm – WL-CSP EEPROM family Microwire Bus

BU9891GUL-W
3) Equivalent circuit
Output circuit
Technical Note
Input citcuit
CS
DO
RESET int.
CSint.
OEint.
Fig.40 Output circuit (DO)
Input circuit
DI
CS int.
Fig.41 Input circuit (CS)
Input circuit
CS int.
SK
Fig.42 Input circuit (DI)
Fig.43 Input circuit (SK)
4) I/O peripheral circuit
4-1) Pull down CS.
By making CS=“L” at power ON/OFF, mistake in operation and mistake write are prevented.
○Pull down resistance Rpd of CS pin
To prevent mistake in operation and mistake write at power ON/OFF, CS pull down resistance is necessary. Select an
appropriate value to this resistance value from microcontroller VOH, IOH, and VIL characteristics of this IC.
Microcontroller
EEPROM
Rpd ≧
VOHM ≧
VOHM
IOHM
VIHE
・・・①
・・・②
VOHM
VIHE
“H” output _IOHM
Rpd
“L” input
Example) When V_CC =5V, VIHE=2V, VOHM=2.4V, IOHM=2mA,
from the equation ①,
Rpd ≧
2.4
2×10^-3
Fig.44 CS pull down resistance
∴ Rpd ≧ 1.2 [kΩ]
With the value of Rpd to satisfy the above equation, VOHM becomes
2.4V or higher, and VIHE (=2.0V), the equation ② is also satisfied.
・VIHE : EEPROM VIH specifications
・VOHM : Microcontroller VOH specifications
・IOHM : Microcontroller IOH specifications
4-2) DO is available in both pull up and pull down.
Do output become “High-Z” in other READY / BUSY output timing than after data output at read command and write
command. When malfunction occurs at “High-Z” input of the microcontroller port connected to DO, it is necessary to
pull down and pull up DO. When there is no influence upon the microcontroller actions, DO may be OPEN.
If DO is OPEN, and at timing to output status READY, at timing of CS=“H”, SK=“H”, DI=“H”, EEPROM recognizes this
as a start bit, resets READY output, and DO=”High-Z”, therefore, READY signal cannot be detected. To avoid such
output, pull up DO pin for improvement.
CS
CS “H”
SK
DI
D0
High-Z
DO
SK
Enlarged
DI
READY
BUSY
DO _BUSY
DO _BUSY
High-Z
CS=SK=DI=”H”
When DO=OPEN
Improvement by DO pull up
READY
CS=SK=DI=”H”
When DO=pull up
Fig.45 READY output timing at DO=OPEN
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11/17
2010.07 - Rev.A