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ICM7170 Datasheet, PDF (6/14 Pages) Intersil Corporation – Microprocessor-Compatible, Real-Time Clock
Timing Diagrams (Continued)
ICM7170
ICM7170
A0 - A4, CS
WR
D0 - D7
ADDRESS VALID, CS LOW
tAD
tWA
tCYC
tWL
tDW
tWD
INPUT DATA VALID
FIGURE 2. WRITE CYCLE TIMING FOR NON-MULTIPLEXED BUS (ALE = VIH, RD = VIH)
A0 - A4, D0 - D7, CS
ALE
RD
ADDRESS VALID, CS LOW
tLA
tLL
tACC
OUTPUT DATA VALID
tAR
tAL
tCYC
tAS
tRD
FIGURE 3. READ CYCLE TIMING FOR MULTIPLEXED BUS (WR = VIH)
A0 - A4, D0 - D7, CS
ALE
WR
ADDRESS VALID, CS LOW
tLL
tAL
tAD
INPUT DATA VALID
tLA
tDW
tWD
tWA
tCYC
tWL
FIGURE 4. WRITE CYCLE TIMING FOR MULTIPLEXED BUS (RD = VIH)
Specification Number5ICM7170_IM (IL) REV -
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